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september 1998 1/86 rev. 2.5 st62t32b st62e32b 8-bit otp/eprom mcus with a/d converter, 16-bit auto-reload timer, eeprom, spi and uart n 3.0 to 6.0v supply operating range n 8 mhz maximum clock frequency n -40 to +125 c operating temperature range n run, wait and stop modes n 5 interrupt vectors n look-up table capability in program memory n data storage in program memory: user selectable size n data ram: 192 bytes n data eeprom: 128 bytes n user programmable options n 30 i/o pins, fully programmable as: input with pull-up resistor input without pull-up resistor input with interrupt generation open-drain or push-pull output analog input n 9 i/o lines can sink up to 20ma to drive leds or triacs directly n 8-bit timer/ counter with 7-bit programmable prescaler n 16-bit auto-reload timer with 7-bit programmable prescaler (ar timer) n digital watchdog n 8-bit a/d converter with 21 analog inputs n 8-bit synchronous peripheral interface (spi) n 8-bit asynchronous peripheral interface (uart) n on-chip clock oscillator can be driven by quartz crystal or ceramic resonator n oscillator safe guard n one external non-maskable interrupt n st623x-emu2 emulation and development system (connects to an ms-dos pc via a parallel port). device summary (see end of datasheet for ordering information) psdip42 pqfp52 cdip42w device otp (bytes) eprom (bytes) i/o pins st62t32b 7948 - 30 st62e32b 7948 30 105
2/86 table of contents 86 document page 106 st62t32b/st62e32b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 general description . . . . . . . ...............................................5 1.1 introduction .........................................................5 1.2 pin descriptions . . . . . . . . . . ............................................7 1.3 memorymap ..........................................................8 1.3.1 introduction . . . . . . . . ................................................8 1.3.2 program space . . . . . . . . . . . . . . . . . . . . . . . . . . . ..........................8 1.3.3 data space . . . . . . . . ...............................................10 1.3.4 stack space . . . . . . . . . . . . . . . . . ......................................10 1.3.5 data window register (dwr) . . . . . . . . . . . . . . . . . . . . .....................11 1.3.6 data ram/eeprom bank register (drbr) ..............................12 1.3.7 eeprom description ...............................................13 1.4 programming modes .................................................15 1.4.1 option byte . . . . . . . . ...............................................15 1.4.2 program memory . . . . ...............................................15 1.4.3 eeprom data memory . . . . . . . . . . . . ..................................15 1.4.4 epromerasing....................................................15 2 central processing unit .................................................16 2.1 introduction ........................................................16 2.2 cpu registers . . . . . . . . ...............................................16 3 clocks, reset, interrupts and power saving modes . . . . . . . ..............18 3.1 clocksystem........................................................18 3.1.1 main oscillator . . . . . . . . . . ...........................................18 3.1.2 low frequency auxiliary oscillator (lfao) . . . . . . . . . . . . . . . ................19 3.1.3 oscillator safe guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................19 3.2 resets...............................................................22 3.2.1 reset input ......................................................22 3.2.2 power-on reset . . . . . . . . . . . . . . . .....................................22 3.2.3 watchdog reset . . . . ...............................................23 3.2.4 application notes . . . . ...............................................23 3.2.5 mcu initialization sequence ..........................................23 3.3 digital watchdog . . . . . . . . . . . . . . . .....................................25 3.3.1 digital watchdog register (dwdr) . . . ..................................27 3.3.2 application notes . . . . ...............................................27 3.4 interrupts . . . . ......................................................29 3.4.1 interrupt request . . . . . . . . . . . . . . . .....................................29 3.4.2 interrupt procedure . . . ..............................................30 3.4.3 interrupt option register (ior) . . . . ....................................31 3.4.4 iinterrupt sources . . . . ...............................................31 3.5 power saving modes .................................................34 3.5.1 wait mode . . . . . . . . ...............................................34 3.5.2 stopmode .......................................................34 3.5.3 exit from wait and stop modes . . . ...................................35
3/86 table of contents document page 107 4 on-chip peripherals . . . ...................................................36 4.1 i/oports.............................................................36 4.1.1 operating modes . . . . ...............................................37 4.1.2 safe i/o state switching sequence . . . ..................................38 4.1.3 artimer alternate functions ..........................................40 4.1.4 spi alternate functions . . . ............................................40 4.1.5 uart alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................40 4.1.6 i/o port option registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................42 4.1.7 i/o port data direction registers . . . ....................................42 4.1.8 i/o port data registers . . . . ..........................................42 4.2 timer ................................................................43 4.2.1 timer operating modes . . . . . . . . . . . . ..................................44 4.2.2 timer interrupt . . . . . . . . . . ...........................................44 4.2.3 application notes . . . . ...............................................45 4.2.4 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .........................45 4.3 artimer 16 . . . ........................................................46 4.3.1 central counter . . . ............................................47 4.3.2 signal generation modes . . . ....................................48 4.3.3 timings measurement modes . . ..................................50 4.3.4 interrupt capabilities ..........................................52 4.3.5 control registers . . . ..........................................53 4.3.6 16-bit registers . . . . . . . . ........................................55 4.4 a/d converter (adc) . . . ..............................................57 4.4.1 application notes . . . . ...............................................57 4.5 u. a. r. t. (universal asynchronous receiver/transmitter). .......... 59 4.5.1 ports interfacing . . . . . . . . . . . . ..................................59 4.5.2 clock generation . . . . ..........................................60 4.5.3 data transmission . . . . . . . . . . . . ..................................60 4.5.4 data reception .................................................61 4.5.5 interrupt capabilities ..........................................61 4.5.6 registers ......................................................61 4.6 serial peripheral interface (spi) . . . . . . . . . . . . ........................63 5software ................................................................65 5.1 st6 architecture . . . . . . . . . . . . . . . .....................................65 5.2 addressing modes . . . . ...............................................65 5.3 instruction set . . . ...................................................66 6 electrical characteristics . . . . . . . . . . . . ..................................71 6.1 absolute maximum ratings . ..........................................71 6.2 recommended operating conditions. . . ..............................72 6.3 dc electrical characteristics ......................................73 6.4 ac electrical characteristics ......................................74 6.5 a/d converter characteristics . . . ...................................74 6.6 timer characteristics . . . ............................................75 6.7 .spi characteristics .................................................75 6.8 artimer16 electrical characteristics . . . . . . . . . . . . . . . ................75
4/86 table of contents 86 document page 108 7 general information . . . . . . . . . . ...........................................76 7.1 package mechanical data . . . . ........................................76 7.2 ordering information ...............................................78 st62p32b . ........................................79 1 general description . . . . . . . ..............................................80 1.1 introduction ........................................................80 1.2 ordering information ...............................................80 1.2.1 transfer of customer code . ..........................................80 1.2.2 listing generation and verification . . . . . . . . . . ...........................80 st6232b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 1 general description . . . . . . . ..............................................84 1.1 introduction ........................................................84 1.2 rom readout protection . . . . . . . . . . . . . . . . . . . . ........................84 1.3 ordering information ...............................................86 1.3.1 transfer of customer code . ..........................................86 1.3.2 listing generation and verification . . . . . . . . . . ...........................86
5/86 st62t32b st62e32b 1 general description 1.1 introduction the st62t32b and st62e32b devices are low cost members of the st62xx 8-bit hcmos family of microcontrollers, which is targeted at low to me- dium complexity applications. all st62xx devices are based on a building block approach: a com- mon core is surrounded by a number of on-chip peripherals. the st62e32b is the erasable eprom version of the st62t32b device, which may be used to em- ulate the st62t32b device, as well as the respec- tive st6232b rom devices. figure 1. block diagram test nmi interrup t program pc stack level 1 stack level 2 stack level 3 stack level 4 stack level 5 stack level 6 power supply oscillator reset data rom user selecta ble data ram port a port b timer digital 8 bit core test/v pp 8-bit a/d converte r pa0..pa1 / 20 ma sink v dd v ss oscin oscout reset watchdog memory port c spi (serial peripheral interfac e) autoreload timer 192 bytes 7948 bytes data eeprom 128 bytes pa2/ovf / 20 ma sink pa3/pwm/20 ma sink pa4/ain/cp1 pa5/ain/cp2 pb0/ain pb3..pb7/ain pc5..pc7/ain port d port e pd0,pd6,pd7/ain pd1/ain/scl pd2/ain/sin pd3/ain/sout pd4/ain/rxd1 pd5/ain/txd1 pe0...pe4 pa6...pa7/ain (vpp on eprom/ot p versions only) timer vr01823e uart 109
6/86 st62t32b st62e32b introduction (cont'd) otp and eprom devices are functionally identi- cal. the rom based versions offer the same func- tionality selecting as rom options the options de- fined in the programmable option byte of the otp/eprom versions.otp devices offer all the advantages of user programmability at low cost, which make them the ideal choice in a wide range of applications where frequent code changes, mul- tiple code versions or last minute programmability are required. figure 2. st62t32b/e32b pin configuration these compact low-cost devices feature a timer comprising an 8-bit counter and a 7-bit program- mable prescaler, an 16-bit auto-reload timer, with 2 input capture channels, eeprom data ca- pability, a serial synchronous port communication interface (spi), a serial asynchronous port inter- face (uart), an 8-bit a/d converter with 21 ana- log inputs and a digital watchdog timer, making them well suited for a wide range of automotive, appliance and industrial applications. figure 3. st62t32b pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 pa0 pa1 pa2/ovf pa3/pwm pa4/ain/cp 1 pa5/ain/cp 2 pa6/ain pa7/ain timer nmi av ss av dd pd0/ain pd1/ain/scl pd2/ain/si n pd3/ain/sout pd4/ain/rxd1 pd5/ain/tx d1 pd6/ain pd7/ain pb0/ain pe4 pe3 pe2 pe1 pe0 oscin oscout ain/cp7 ain/pc6 ain/pc5 v ssp v ddp v ss v dd test/v pp (1) reset ain/pb7 ain/pb6 ain/pb5 ain/pb4 ain/pb3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 1. v pp on eprom/otp only vr01375g 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 32 31 30 29 28 27 33 141516171819202122232425 26 52515049484746454443424140 nc oscin oscout ain/pc7 ain/pc6 ain/pc5 nc v ssp v ddp v ss v dd test/v pp (1) reset pa4/ain/cp1 pa5/ain/cp2 pa6/ain pa7/ain timer nmi av ss av dd pd0/ain pd1/ain/scl pd2/ain/sin pd3/ain/sout nc pe0 pe1 pe2 pe3 pe4 nc nc nc pa0 pa1 pa2/ovf pa3/pwm nc ain/pb7 ain/pb6 ain/pb5 ain/pb4 ain/pb3 nc nc ain/pb0 ain/pd7 ain/pd6 ain/pd5/txd1 ain/pd4/rxd1 nc 1. v pp on eprom/otp only vr02008a 110
7/86 st62t32b st62e32b 1.2 pin descriptions v dd and v ss . power is supplied to the mcu via these two pins. v dd is the power connection and v ss is the ground connection. v ddp and v ssp . power is supplied to the mcu i/os independently from the rest of the chip using these two pins. these pins have to be connected to the vdd and vss pins. it is not allowed to leave any of these pins unconnected or to apply different potentials respectively to v dd /v ddp and v ss /v ssp . av dd and av ss . power is supplied to the mcua/d converter independently from the rest of the chip using these two pins. oscin and oscout. these pins are internally connected to the on-chip oscillator circuit. a quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins. the oscin pin is the input pin, the oscout pin is the output pin. reset . the active-low reset pin is used to re- start the microcontroller. test/v pp . the test must be held at v ss for nor- mal operation. if test pin is connected to a +12.5v level during the reset phase, the eprom/otp programming mode is entered. nmi. the nmi pin provides the capability for asyn- chronous interruption, by applying an external non maskable interrupt to the mcu. the nmi input is falling edge sensitive with schmitt trigger charac- teristics. the user can select as option the availa- bility of an on-chip pull-up at this pin. pa0-pa7. these 8 lines are organised as one i/o port (a). each line may be configured under soft- ware control as inputs with or without internal pull- up resistors, interrupt generating inputs with pull- up resistors, open-drain or push-pull outputs. pa2/ovf, pa3/pwm, pa4/cp1 and pa5/cp2 can be used respectively as overflow output pin, output compare pin, and as two input capture pins for the embedded 16-bit auto-reload timer. in addition, pa4-pa5 can also be used as analog inputs for the a/d converter while pa0-pa3 can sink 20ma for direct led or triac drive. pb0,pb3-pb7 these 6 lines are organised as one i/o port (b). each line may be configured under software control as inputs with or without internal pull-up resistors, interrupt generating inputs with pull-up resistors, open-drain or push-pull outputs, analog inputs for the a/d converter. pc5-pc7 . these 3 lines are organised as one i/o port (c). each line may be configured under soft- ware control as input with or without internal pull- up resistor, interrupt generating input with pull-up resistor, analog input for the a/d converter, open- drain or push-pull output. pd0-pd7 . these 8 lines are organised as one i/o port (portd). each line may be configured under software control as input with or without internal pull-up resistor, interrupt generating input with pull-up resistor, analog input open-drain or push- pull output. in adition, the pins pd5/txd1 and pd4/rxd1 can be used as uart output (pd5/txd1) or uart input (pd4/rxd1). the pins pd3/sout, pd2/sin and pd1/scl can also be used respectively as data out, data in and clock pins for the on-chip spi. pe0-pe4 . these 5 lines are organised as one i/o port (pe). each line may be configured under soft- ware control as input with or without internal pull- up resistor, interrupt generation input with pull-up resistor, open-drain or push-pull output. in output mode, these lines can also sink 20ma for direct led and triac driving. timer . this is the timer 1 i/o pin. in input mode, it is connected to the prescaler and acts as ex- ternal timer clock or as control gate for the internal timer clock. in output mode, the timer pin outputs the data bit when a time-out occurs.the user can select as option the availability of an on-chip pull- up at this pin. 111
8/86 st62t32b st62e32b 1.3 memory map 1.3.1 introduction the mcu operates in three separate memory spaces: program space, data space, and stack space. operation in these three memory spaces is described in the following paragraphs. briefly, program space contains user program code in program memory and user vectors; data space contains user data in ram and in program memory, and stack space accommodates six lev- els of stack for subroutine and interrupt service routine nesting. 1.3.2 program space program space comprises the instructions to be executed, the data required for immediate ad- dressing mode instructions, the reserved factory test area and the user vectors. program space is addressed via the 12-bit program counter register (pc register). program space is organised in four 2k pages. three of them are addressed in the 000h-7ffh lo- cations of the program space by the program counter and by writing the appropriate code in the program rom page register (prpr register). a common (static) 2k page is available all the time for interrupt vectors and common subrou- tines, independently of the prpr register content. this astatico page is directly addressed in the 0800h-0fffh by the msb of the program counter register pc 11. note this page can also be ad- dressed in the 000-7ffh range. it is two different ways of addressing the same physical memory. jump from a dynamic page to another dynamic page is achieved by jumping back to the static page, changing contents of prpr and then jump- ing to the new dynamic page. figure 4. 8kbytes program space addressing figure 5. memory addressing diagram pc space 000h 7ffh 800h fffh 0000h 1fffh page 0 page 1 static page page 2 page 3 page 1 static page rom space program space program interrupt & reset vectors accumulator data ram bank select window select ram x register y register v register w register data read-only window ram / eeprom banking area 000h 03fh 040h 07fh 080h 081h 082h 083h 084h 0c0h 0ffh 0-63 data space 0000h 0ff0h 0fffh memory memory data read-only memory vr01568 112
9/86 st62t32b st62e32b memory map (cont'd) table 1. st62e32b/t32b program memory map note : otp/eprom devices can be programmed with the development tools available from stmicro- electronics (st62e3x-epb or st623x-kit). 1.3.2.1 program rom page register (prpr) the prpr register can be addressed like a ram location in the data space at the address cah ; nevertheless it is a write only register that cannot be accessed with single-bit operations. this regis- ter is used to select the 2-kbyte rom bank of the program space that will be addressed. the number of the page has to be loaded in the prpr register. refer to the program space description for additional information concerning the use of this register. the prpr register is not modified when an interrupt or a subroutine occurs. care is required when handling the prpr register as it is write only. for this reason, it is not allowed to change the prpr contents while executing in- terrupt service routine, as the service routine cannot save and then restore its previous content. this operation may be necessary if common rou- tines and interrupt service routines take more than 2k bytes ; in this case it could be necessary to di- vide the interrupt service routine into a (minor) part in the static page (start and end) and to a second (major) part in one of the dynamic pages. if it is im- possible to avoid the writing of this register in inter- rupt service routines, an image of this register must be saved in a ram location, and each time the program writes to the prpr it must write also to the image register. the image register must be written before prpr, so if an interrpt occurs between the two instructions the prpr is not af- fected. program rom page register (prpr) address: cah e write only bits 2-7= not used. bit 5-0 = prpr1-prpr0: program rom select. these two bits select the corresponding page to be addressed in the lower part of the 4k program address space as specified intable 2. this register is undefined on reset. neither read nor single bit instructions may be used to address this register. table 2. 8kbytes program rom page register coding 1.3.2.2 program memory protection the program memory in otp or eprom devices can be protected against external readout of mem- ory by selecting the readout protection op- tion in the option byte. in the eprom parts, readout protection option can be disactivated only by u.v. erasure that also results into the whole eprom context erasure. note: once the readout protection is activated, it is no longer possible, even for stmicroelectronics, to gain access to the program memory contents. returned parts with a protection set can therefore not be accepted. rom page device address description page 0 0000h-007fh 0080h-07ffh reserved user rom page 1 astatico 0800h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh user rom reserved interrupt vectors reserved nmi vector reset vector page 2 0000h-000fh 0010h-07ffh reserved user rom page 3 0000h-000fh 0010h-07ffh reserved user rom 70 - - - - - - prpr0 prpr1 prpr1 prpr0 pc bit 11 memory page x x 1 static page (page 1) 0 0 0 page 0 0 1 0 page 1 (static page 1 0 0 page 2 1 1 0 page 3 113
10/86 st62t32b st62e32b memory map (cont'd) 1.3.3 data space data space accommodates all the data necessary for processing the user program. this space com- prises the ram resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in program memory. 1.3.3.1 data rom all read-only data is physically stored in program memory, which also accommodates the program space. the program memory consequently con- tains the program code to be executed, as well as the constants and look-up tables required by the application. the data space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in program memory. 1.3.3.2 data ram/eeprom in st6232b and st62e32b devices, the data space includes 60 bytes of ram, the accumulator (a), the indirect registers (x), (y), the short direct registers (v), (w), the i/o port registers, the pe- ripheral data and control registers, the interrupt option register and the data rom window register (drw register). additional ram and eeprom pages can also be addressed using banks of 64 bytes located between addresses 00h and 3fh. 1.3.4 stack space stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents. table 3. additional ram/eeprom banks. table 4. st62t32b/e32b data memory space device ram eeprom st62t32b/e32b 2 x 64 bytes 2 x 64 bytes data and eeprom 000h 03fh data rom window area 040h 07fh x register 080h y register 081h v register 082h w registe r 083h data ram 084h 0bfh port a data register 0c0h port b data register 0c1h port c data register 0c2h port d data register 0c3h port a direction register 0c4h port b direction register 0c5h port c direction register 0c6h port d direction register 0c7h interrupt option register 0c8h* data rom wind ow register 0c9h* rom bank select register 0cah* ram/eeprom bank select register 0cbh* port a option register 0cch port b option register 0cdh port c option registe r 0ceh port d option registe r 0cfh a/d data registe r 0d0h a/d control register 0d1h timer 1 prescaler register 0d2h timer 1 counte r register 0d3h timer 1 status/control register 0d4h reserved 0d5h uart data shift register 0d6h uart status control register 0d7h watchdog register 0d8h reserved 0d9h i/o interrupt polarity register 0dah oscillator control register 0dbh spi interrupt disable register 0dch* spi data register 0ddh reserved 0deh eeprom control register 0dfh artim16 compare mask reg. low byte mask 0e0h artim16 2nd status control registe r scr2 0e1h artim16 3rd status control registe r scr3 0e2h artim16 4th status control register scr4 0e3h artim16 1st status control register scr1 0e8h artim16 reload capture reg. high byte rlcp 0e9h artim16 reload capture reg. low byte rlcp 0eah artim16 capt ure register high byte cp 0ebh artim16 capture register low byte cp 0ech artim16 comparevalue register high bytecmp 0edh artim 16 compare value register lowbyte cmp 0eeh arti m 16 compare mask reg. high byte mask 0efh reserved 0f0h 0fbh port e data register ofch port e direction regist er 0fdh port e option register 0feh accumulator offh * write only register 114
11/86 st62t32b st62e32b memory map (cont'd) 1.3.5 data window register (dwr) the data read-only memory window is located from address 0040h to address 007fh in data space. it allows direct reading of 64 consecutive bytes locat- ed anywhere in program memory, between ad- dress 0000h and 1fffh (top memory address de- pends on the specific device). all the program memory can therefore be used to store either in- structions or read-only data. indeed, the window can be moved in steps of 64 bytes along the pro- gram memory by writing the appropriate code in the data window register (dwr). the dwr can be addressed like any ram location in the data space, it is however a write-only regis- ter and therefore cannot be accessed using single- bit operations. this register is used to position the 64-byte read-only data window (from address 40h to address 7fh of the data space) in program memory in 64-byte steps. the effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the register address given in the instruction (as least significant bits) and the content of the dwr register (as most significant bits), as illustrat- ed in figure 6 below. for instance, when address- ing location 0040h of the data space, with 0 load- ed in the dwr register, the physical location ad- dressed in program memory is 00h. the dwr reg- ister is not cleared on reset, therefore it must be written to prior to the first access to the data read- only memory window area. data window register (dwr) address: 0c9h e write only bits 7 = not used. bit 6-0 = dwr5-dwr0: data read-only memory window register bits. these are the data read- only memory window bits that correspond to the upper bits of the data read-only memory space. caution: this register is undefined on reset. nei- ther read nor single bit instructions may be used to address this register. note: care is required when handling the dwr register as it is write only. for this reason, the dwr contents should not be changed while exe- cuting an interrupt service routine, as the service routine cannot save and then restore the register's previous contents. if it is impossible to avoid writ- ing to the dwr during the interrupt service routine, an image of the register must be saved in a ram location, and each time the program writes to the dwr, it must also write to the image register. the image register must be written first so that, if an in- terrupt occurs between the two instructions, the dwr is not affected. figure 6. data read-only memory window memory addressing 70 - dwr6 dwr5 dwr4 dwr3 dwr2 dwr1 dwr0 data rom window register contents data space address 40h-7fh in instruction program space address 765432 0 543210 543210 read 1 6 7 8 9 10 11 0 1 vr0a1573 12 1 0 data space address 59h 0 0 0 0 0 1 00 1 1 1 example: (dwr) dwr=28h 11 0000 00 00 1 rom address:a19h 11 13 01 115
12/86 st62t32b st62e32b memory map (cont'd) 1.3.6 data ram/eeprom bank register (drbr) address: cbh e write only bit 7-5 = these bits are not used bit 4 - drbr4 . this bit, when set, selects ram page 2. bit 3 - drbr3 . this bit, when set, selects ram page 1. bit2. this bit is not used. bit 1 - drbr1 . this bit, when set, selects eeprom page 1. bit 0 - drbr0 . this bit, when set, selects eeprom page 0. the selection of the bank is made by programming the data ram bank switch register (drbr regis- ter) located at address cbh of the data space ac- cording to table 1. no more than one bank should be set at a time. the drbr register can be addressed like a ram data space at the address cbh; nevertheless it is a write only register that cannot be accessed with single-bit operations. this register is used to select the desired 64-byte ram/eeprom bank of the data space. the number of banks has to be load- ed in the drbr register and the instruction has to point to the selected location as if it was in bank 0 (from 00h address to 3fh address). this register is not cleared during the mcu initiali- zation, therefore it must be written before the first access to the data space bank region. refer to the data space description for additional informa- tion. the drbr register is not modified when an interrupt or a subroutine occurs. notes : care is required when handling the drbr register as it is write only. for this reason, it is not allowed to change the drbr contents while executing in- terrupt service routine, as the service routine can- not save and then restore its previous content. if it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a ram location, and each time the program writes to drbr it must write also to the image register. the image register must be written first, so if an interrupt occurs between the two instructions the drbr is not affected. in drbr register, only 1 bit must be set. other- wise two or more pages are enabled in parallel, producing errors. table 5. data ram bank register set-up 70 - - - drbr4 drbr3 - drbr1 drbr0 drbr st62t32b/e32b 00 none 01 eeprom page 0 02 eeprom page 1 08 ram page 1 10h ram page 2 other reserved 116
13/86 st62t32b st62e32b memory map (cont'd) 1.3.7 eeprom description eeprom memory is located in 64-byte pages in data space. this memory may be used by the user program for non-volatile data storage. data space from 00h to 3fh is paged as described in table 6. eeprom locations are accessed di- rectly by addressing these paged sections of data space. the eeprom does not require dedicated instruc- tions for read or write access. once selected via the data ram bank register, the active eeprom page is controlled by the eeprom control regis- ter (eectl), which is described below. bit e20ff of the eectl register must be reset prior to any write or read access to the eeprom. if no bank has been selected, or if e2off is set, any ac- cess is meaningless. programming must be enabled by setting the e2ena bit of the eectl register. the e2busy bit of the eectl register is set when the eeprom is performing a programming cycle. any access to the eeprom when e2busy is set is meaningless. provided e2off and e2busy are reset, an eep- rom location is read just like any other data loca- tion, also in terms of access time. writing to the eeprom may be carried out in two modes: byte mode (bmode) and parallel mode (pmode). in bmode, one byte is accessed at a time, while in pmode up to 8 bytes in the same row are programmed simultaneously (with conse- quent speed and power consumption advantages, the latter being particularly important in battery powered circuits). general notes : data should be written directly to the intended ad- dress in eeprom space. there is no buffer mem- ory between data ram and the eeprom space. when the eeprom is busy (e2busy = a1o) eectl cannot be accessed in write mode, it is only possible to read the status of e2busy. this implies that as long as the eeprom is busy, it is not possible to change the status of the eeprom control register. eectl bits 4 and 5 are reserved and must never be set. care is required when dealing with the eectl reg- ister, as some bits are write only. for this reason, the eectl contents must not be altered while ex- ecuting an interrupt service routine. if it is impossible to avoid writing to this register within an interrupt service routine, an image of the register must be saved in a ram location, and each time the program writes to eectl it must also write to the image register. the image register must be written to first so that, if an interrupt oc- curs between the two instructions, the eectl will not be affected. table 6. row arrangement for parallel writing of eeprom locations dataspace addresses. banks 0 and 1. byte 01234567 row7 38h-3fh row6 30h-37h row5 28h-2fh row4 20h-27h row3 18h-1fh row2 10h-17h row1 08h-0fh row0 00h-07h up to 8 bytes in each row may be programmed simultaneously in parallel write mode. the number of available 64-byte banks (1 or 2) is device dependent. 117
14/86 st62t32b st62e32b memory map (cont'd) additional notes on parallel mode: if the user wishes to perform parallel program- ming, the first step should be to set the e2par2 bit. from this time on, the eeprom will be ad- dressed in write mode, the row address will be latched and it will be possible to change it only at the end of the programming cycle, or by resetting e2par2 without programming the eeprom. af- ter the row address is latched, the mcu can only aseeo the selected eeprom row and any attempt to write or read other rows will produce errors. the eeprom should not be read while e2par2 is set. as soon as the e2par2 bit is set, the 8 volatile row latches are cleared. from this moment on, the user can load data in all or in part of the row. setting e2par1 will modify the eeprom regis- ters corresponding to the row latches accessed after e2par2. for example, if the software sets e2par2 and accesses the eeprom by writing to addresses 18h, 1ah and 1bh, and then sets e2par1, these three registers will be modified si- multaneously; the remaining bytes in the row will be unaffected. note that e2par2 is internally reset at the end of the programming cycle. this implies that the user must set the e2par2 bit between two parallel pro- gramming cycles. note that if the user tries to set e2par1 while e2par2 is not set, there will be no programming cycle and the e2par1 bit will be un- affected. consequently, the e2par1 bit cannot be set if e2ena is low. the e2par1 bit can be set by the user, only if the e2ena and e2par2 bits are also set. eeprom control register (eectl) address: dfh e read/write reset status: 00h bit 7 = d7 : unused. bit 6 = e2off : stand-by enable bit. write only. if this bit is set the eeprom is disabled (any access will be meaningless) and the power consumption of the eeprom is reduced to its lowest value. bit 5-4 = d5-d4 : reserved. must be kept reset. bit 3 = e2par1 : parallel start bit. write only. once in parallel mode, as soon as the user software sets the e2par1 bit, parallel writing of the 8 adja- cent registers will start. this bit is internally reset at the end of the programming procedure. note that less than 8 bytes can be written if required, the un- defined bytes being unaffected by the parallel pro- gramming cycle; this is explained in greater detail in the additional notes on parallel mode overleaf. bit 2 = e2par2 : parallel mode en. bit. write only. this bit must be set by the user program in order to perform parallel programming. if e2par2 is set and the parallel start bit (e2par1) is reset, up to 8 adjacent bytes can be written simultane- ously. these 8 adjacent bytes are considered as a row, whose address lines a7, a6, a5, a4, a3 are fixed while a2, a1 and a0 are the changing bits, as illustrated in table 6. e2par2 is automatically re- set at the end of any parallel programming proce- dure. it can be reset by the user software before starting the programming procedure, thus leaving the eeprom registers unchanged. bit 1 = e2busy : eeprom busy bit. read on- ly. this bit is automatically set by the eeprom control logic when the eeprom is in program- ming mode. the user program should test it before any eeprom read or write operation; any attempt to access the eeprom while the busy bit is set will be aborted and the writing procedure in progress will be completed. bit 0 = e2ena : eeprom enable bit. write on- ly. this bit enables programming of the eeprom cells. it must be set before any write to the eep- rom register. any attempt to write to the eep- rom when e2ena is low is meaningless and will not trigger a write cycle. 70 d7 e2off d5 d4 e2par1 e2par2 e2busy e2ena 118
15/86 st62t32b st62e32b 1.4 programming modes 1.4.1 option byte the option byte allows configuration capability to the mcus. option byte's content is automatically read, and the selected options enabled, when the chip reset is activated. it can only be accessed during the programming mode. this access is made either automatically (copy from a master device) or by selecting the option byte programming mode of the pro- grammer. the option byte is located in a non-user map. no address has to be specified. eprom code option byte bit 7. reserved. bit 6 = port pull . this bit must be set high to have pull-up input state at reset on the i/o port. when this bit is low, i/o ports are in input without pull-up (high impedance) state at reset bit 5 = extcntl . this bit selects the external stop mode capability. when extcntl is high, pin nmi controls if the stop mode can be ac- cessed when the watchdog is active. when extc- ntl is low, the stop instruction is processed as a wait as soon as the watchdog is active. bit 4 = protect . this bit allows the protection of the software contents against piracy. when the bit protect is set high, readout of the otp con- tents is prevented by hardware. no programming equipment is able to gain access to the user pro- gram. when this bit is low, the user program can be read. bit 3 = tim pull. this bit must be set high to con- figure the timer pin with a pull up resistor. when it is low, no pull up is provided. bit 2 = nmi pull. this bit must be set high to con- figure the nmi pin with a pull up resistor when it is low, no pull up is provided. bit 1 = wdact . this bit controls the watchdog ac- tivation. when it is high, hardware activation is se- lected. the software activation is selected when wdact is low. bit 0 = osgen. this bit must be set high to enable the oscillator safe guard. when this bit is low, the osg is disabled. the option byte is written during programming ei- ther by using the pc menu (pc driven mode) or automatically (stand-alone mode) 1.4.2 program memory eprom/otp programming mode is set by a +12.5v voltage applied to the test/v pp pin. the programming flow of the st62t32b/e32b is de- scribed in the user manual of the eprom pro- gramming board. the mcus can be programmed with the st62e3xb eprom programming tools available from stmicroelectronics. 1.4.3 eeprom data memory eeprom data pages are supplied in the virgin state ffh. partial or total programming of eep- rom data memory can be performed either through the application software, or through an ex- ternal programmer. any stmicroelectronics tool used for the program memory (otp/eprom) can also be used to program the eeprom data mem- ory. 1.4.4 eprom erasing the eprom of the windowed package of the mcus may be erased by exposure to ultra violet light. the erasure characteristic of the mcus is such that erasure begins when the memory is ex- posed to light with a wave lengths shorter than ap- proximately 4000?. it should be noted that sun- lights and some types of fluorescent lamps have wavelengths in the range 3000-4000?. it is thus recommended that the window of the mcus packages be covered by an opaque label to prevent unintentional erasure problems when test- ing the application in such an environment. the recommended erasure procedure of the mcus eprom is the exposure to short wave ul- traviolet light which have a wave-length 2537a. the integrated dose (i.e. u.v. intensity x exposure time) for erasure should be a minimum of 15w- sec/cm 2 . the erasure time with this dosage is ap- proximately 15 to 20 minutes using an ultraviolet lamp with 12000 m w/cm 2 power rating. the st62e32b should be placed within 2.5cm (1inch) of the lamp tubes during erasure. 70 - port pull extc ntl protect tim pull nmi pull wdact osgen 119
16/86 st62t32b st62e32b 2 central processing unit 2.1 introduction the cpu core of st6 devices is independent of the i/o or memory configuration. as such, it may be thought of as an independent central processor communicating with on-chip i/o, memory and pe- ripherals via internal address, data, and control buses. in-core communication is arranged as shown in figure 7; the controller being externally linked to both the reset and oscillator circuits, while the core is linked to the dedicated on-chip pe- ripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers. 2.2 cpu registers the st6 family cpu core features six registers and three pairs of flags available to the programmer. these are described in the following paragraphs. accumulator (a) . the accumulator is an 8-bit general purpose register used in all arithmetic cal- culations, logical operations, and data manipula- tions. the accumulator can be addressed in data space as a ram location at address ffh. thus the st6 can manipulate the accumulator just like any other register in data space. indirect registers (x, y). these two indirect reg- isters are used as pointers to memory locations in data space. they are used in the register-indirect addressing mode. these registers can be ad- dressed in the data space as ram locations at ad- dresses 80h (x) and 81h (y). they can also be ac- cessed with the direct, short direct, or bit direct ad- dressing modes. accordingly, the st6 instruction set can use the indirect registers as any other reg- ister of the data space. short direct registers (v, w). these two regis- ters are used to save a byte in short direct ad- dressing mode. they can be addressed in data space as ram locations at addresses 82h (v) and 83h (w). they can also be accessed using the di- rect and bit direct addressing modes. thus, the st6 instruction set can use the short direct regis- ters as any other register of the data space. program counter (pc). the program counter is a 12-bit register which contains the address of the next rom location to be processed by the core. this rom location may be an opcode, an oper- and, or the address of an operand. the 12-bit length allows the direct addressing of 4096 bytes in program space. figure 7. st6 core block diagram program reset opcode flag values 2 controller flags alu a-data b-data address /read line data space interr upts data ram/eeprom data rom/epr om results to data space (write line) rom/eprom dedications accumulator control signals oscin oscout address decoder 256 12 program counter and 6 layer stack 0,01 to 8mhz vr01811 120
17/86 st62t32b st62e32b cpu registers (cont'd) however, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the program bank switch register. the pc value is incremented after reading the ad- dress of the current instruction. to execute relative jumps, the pc and the offset are shifted through the alu, where they are added; the result is then shifted back into the pc. the program counter can be changed in the following ways: - jp (jump) instructionpc=jump address - call instructionpc= call address - relative branch instruction.pc= pc +/- offset - interrupt pc=interrupt vector - reset pc= reset vector - ret & reti instructionspc= pop (stack) - normal instructionpc= pc + 1 flags (c, z) . the st6 cpu includes three pairs of flags (carry and zero), each pair being associated with one of the three normal modes of operation: normal mode, interrupt mode and non maskable interrupt mode. each pair consists of a carry flag and a zero flag. one pair (cn, zn) is used during normal operation, another pair is used dur- ing interrupt mode (ci, zi), and a third pair is used in the non maskable interrupt mode (cnmi, zn- mi). the st6 cpu uses the pair of flags associated with the current mode: as soon as an interrupt (or a non maskable interrupt) is generated, the st6 cpu uses the interrupt flags (resp. the nmi flags) instead of the normal flags. when the reti in- struction is executed, the previously used set of flags is restored. it should be noted that each flag set can only be addressed in its own context (non maskable interrupt, normal interrupt or main rou- tine). the flags are not cleared during context switching and thus retain their status. the carry flag is set when a carry or a borrow oc- curs during arithmetic operations; otherwise it is cleared. the carry flag is also set to the value of the bit tested in a bit test instruction; it also partici- pates in the rotate left instruction. the zero flag is set if the result of the last arithme- tic or logical operation was equal to zero; other- wise it is cleared. switching between the three sets of flags is per- formed automatically when an nmi, an interrupt or a reti instructions occurs. as the nmi mode is automatically selected after the reset of the mcu, the st6 core uses at first the nmi flags. stack. the st6 cpu includes a true lifo hard- ware stack which eliminates the need for a stack pointer. the stack consists of six separate 12-bit ram locations that do not belong to the data space ram area. when a subroutine call (or inter- rupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the pc is shifted into the first level (the original contents of the sixth stack level are lost). when a subroutine or interrupt return occurs (ret or reti instructions), the first level register is shifted back into the pc and the value of each level is popped back into the previous level. since the accumula- tor, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subrou- tine. the stack will remain in its adeepesto position if more than 6 nested calls or interrupts are execut- ed, and consequently the last return address will be lost. it will also remain in its highest position if the stack is empty and a ret or reti is executed. in this case the next instruction will be executed. figure 8. st6 cpu programming mode l short direct addressing mode v register wregister program counter six levels stack register cz normal flags interrupt flags nmi flags index register va000423 b7 b7 b7 b7 b7 b0 b0 b0 b0 b0 b0 b11 accumulator yreg.pointer xreg.pointer cz cz 121
18/86 st62t32b st62e32b 3 clocks, reset, interrupts and power saving modes 3.1 clock system the mcu features a main oscillator which can be driven by an external clock, or used in conjunction with an at-cut parallel resonant crystal or a suita- ble ceramic resonator. in addition, a low frequen- cy auxiliary oscillator (lfao) can be switched in for security reasons, to reduce power consump- tion, or to offer the benefits of a back-up clock sys- tem. the oscillator safeguard (osg) option filters spikes from the oscillator lines, provides access to the lfao to provide a backup oscillator in the event of main oscillator failure and also automati- cally limits the internal clock frequency (f int )asa function of v dd , in order to guarantee correct oper- ation. these functions are illustrated in figure 10, figure 11, figure 12 and figure 13. figure 9 illustrates various possible oscillator con- figurations using an external crystal or ceramic res- onator, an external clock input or the lowest cost so- lution using only the lfao. c l1 an c l2 should have a capacitance intherange 12 to22 pfforanoscillator frequency in the 4-8 mhz range. the internal mcu clock frequency (f int ) is divided by 12 to drive the timer and the watchdog timer, and by 13 to drive the cpu core, while the a/d converter is driven by f int divided either by 6 or by 12 as may be seen in figure 12. with an 8mhz oscillator frequency, the fastest ma- chine cycle is therefore 1.625 m s. a machine cycle is the smallest unit of time needed to execute any operation (for instance, to increment the program counter). an instruction may require two, four, or five machine cycles for execution. 3.1.1 main oscillator the main oscillator can be turned off (when the osg enabled option is selected) by setting the oscoff bit of the oscr control register. the low frequency auxiliary oscillator is automatical- ly started. figure 9. oscillator configurations integrate d clock osg enabled option osc in osc out c l1n c l2 st6xxx crystal/r esonator clock osc in osc out st6xxx external clock nc osc in osc out st6xxx nc va0016 va0015a 122
19/86 st62t32b st62e32b clock system (cont'd) turning on the main oscillator is achieved by re- setting the oscoff bit of the oscr register or by resetting the mcu. restarting the main oscilla- tor implies a delay comprising the oscillator start up delay period plus the duration of the software instruction at f lfao clock frequency. 3.1.2 low frequency auxiliary oscillator (lfao) the low frequency auxiliary oscillator has three main purposes. firstly, it can be used to reduce power consumption in non timing critical routines. secondly, it offers a fully integrated system clock, without any external components. lastly, it acts as a safety oscillator in case of main oscillator failure. this oscillator is available when the osg ena- bled option is selected. in this case, it automati- cally starts one of its periods after the first missing edge from the main oscillator, whatever the reason (main oscillator defective, no clock circuitry provid- ed, main oscillator switched off...). user code, normal interrupts, wait and stop in- structions, are processed as normal, at the re- duced f lfao frequency. the a/d converter accura- cy is decreased, since the internal frequency is be- low 1mhz. at power on, the low frequency auxiliary oscilla- tor starts faster than the main oscillator. it there- fore feeds the on-chip counter generating the por delay until the main oscillator runs. the low frequency auxiliary oscillator is auto- matically switched off as soon as the main oscilla- tor starts. oscr address: 0dbh e read/write bit 7-1= these bits are not used and must be kept cleared after reset. bit 0 = oscoff . main oscillator turn-off. when low, this bit enables main oscillator to run. the main oscillator is switched off when oscoff is high. 3.1.3 oscillator safe guard the oscillator safe guard (osg) affords drastical- ly increased operational integrity in st62xx devic- es. the osg circuit provides three basic func- tions: it filters spikes from the oscillator lines which would result in over frequency to the st62 cpu; it gives access to the low frequency auxiliary os- cillator (lfao), used to ensure minimum process- ing in case of main oscillator failure, to offer re- duced power consumption or to provide a fixed fre- quency low cost oscillator; finally, it automatically limits the internal clock frequency as a function of supply voltage, in order to ensure correct opera- tion even if the power supply should drop. the osg is enabled or disabled by choosing the relevant osg option. it may be viewed as a filter whose cross-over frequency is device dependent. spikes on the oscillator lines result in an effectively increased internal clock frequency. in the absence of an osg circuit, this may lead to an over fre- quency for a given power supply voltage. the osg filters out such spikes (as illustrated in fig- ure 10). in all cases, when the osg is active, the maximum internal clock frequency, f int , is limited to f osg , which is supply voltage dependent. this relationship is illustrated in figure 13. when the osg is enabled, the low frequency auxiliary oscillator may be accessed. this oscilla- tor starts operating after the first missing edge of the main oscillator (see figure 11). over-frequency, at a given power supply level, is seen by the osg as spikes; it therefore filters out some cycles in order that the internal clock fre- quency of the device is kept within the range the particular device can stand (depending on v dd ), and below f osg : the maximum authorised frequen- cy with osg enabled. note. the osg should be used wherever possible as it provides maximum safety. care must be tak- en, however, as it can increase power consump- tion and reduce the maximum operating frequency to f osg . 70 ------- osc off 123
20/86 st62t32b st62e32b clock system (cont'd) figure 10. osg filtering principle figure 11. osg emergency oscillator principle (1) vr001932 (3) (2) (4) (1) (2) (3) (4) maximum frequency for the device to work correctly actual quartz crystal frequency at oscin pin noise from oscin resulting internal frequency main vr001933 internal emergency oscillator frequency oscillator 124
21/86 st62t32b st62e32b clock system (cont'd) figure 12. clock circuit block diagram figure 13. maximum operating frequency (f max ) versus supply voltage (v dd ) notes : 1. in this area, operation is guaranteed at the quartz crystal frequency. 2. when the osg is disabled, operation in this area is guaranteed at the crystal frequency. when the osg is enabled, operation in this area is guaranteed at a frequency of at least f osg min. 3. when the osg is disabled, operation in this area is guaranteed at the quartz crystal frequency. when the osg is enabled, access to this area is prevented. the internal frequency is kept a f osg. 4. when the osg is disabled, operation in this area is not guaranteed when the osg is enabled, access to this area is prevented. the internal frequency is kept at f osg. main oscillator osg lfao m u x core :13 :12 :1 timer 1 watchdog por f int main oscillator off adc artimer 16 :6 m u x 1 2.5 3.5 4 4.5 5 5.5 6 8 7 6 5 4 3 2 maximum frequency (mhz) supply voltage (v dd ) functionality is not 3 4 3 2 1 f osg f osg min guaranteed in this area vr01807 125
22/86 st62t32b st62e32b 3.2 resets the mcu can be reset in three ways: by the external reset input being pulled low; by power-on reset; by the digital watchdog peripheral timing out. 3.2.1 reset input the reset pin may be connected to a device of the application board in order to reset the mcu if required. the reset pin may be pulled low in run, wait or stop mode. this input can be used to reset the mcu internal state and ensure a correct start-up procedure. the pin is active low and features a schmitt trigger input. the internal reset signal is generated by adding a delay to the external signal. therefore even short pulses on the reset pin are acceptable, provided v dd has completed its rising phase and that the oscillator is running correctly (normal run or wait modes). the mcu is kept in the reset state as long as the reset pin is held low. if reset activation occurs in the run or wait modes, processing of the user program is stopped (run mode only), the inputs and outputs are con- figured as inputs with pull-up resistors and the main oscillator is restarted. when the level on the reset pin then goes high, the initialization se- quence is executed following expiry of the internal delay period. if reset pin activation occurs in the stop mode, the oscillator starts up and all inputs and outputs are configured as inputs with pull-up resistors. when the level of the reset pin then goes high, the initialization sequence is executed following expiry of the internal delay period. 3.2.2 power-on reset the function of the por circuit consists in waking up the mcu at an appropriate stage during the power-on sequence. at the beginning of this se- quence, the mcu is configured in the reset state: all i/o ports are configured as inputs with pull-up resistors and no instruction is executed. when the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. the initialization sequence is executed immediate- ly following the internal delay. the internal delay is generated by an on-chip coun- ter. the internal reset line is released 2048 internal clock cycles after release of the external reset. notes: to ensure correct start-up, the user should take care that the reset signal is not released before the v dd level is sufficient to allow mcu operation at the chosen frequency (see recommended oper- ating conditions). a proper reset signal for a slow rising v dd supply can generally be provided by an external rc net- work connected to the reset pin. figure 14. reset and interrupt processing int latch cleared nmi mask set reset ( if present ) select nmi mode flags is reset still present? yes put ffeh on address bus from reset locations ffe/f ff no fetch instruction load pc va000427 126
23/86 st62t32b st62e32b resets (cont'd) 3.2.3 watchdog reset the mcu provides a watchdog timer function in order to ensure graceful recovery from software upsets. if the watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. this, amongst oth- er things, resets the watchdog counter. the mcu restarts just as though the reset had been generated by the reset pin, including the built-in stabilisation delay period. 3.2.4 application notes no external resistor is required between v dd and the reset pin, thanks to the built-in pull-up device. the por circuit operates dynamically, in that it triggers mcu initialization on detecting the rising edge of v dd . the typical threshold is in the region of 2 volts, but the actual value of the detected threshold depends on the way in which v dd rises. the por circuit is not designed to supervise static, or slowly rising or falling v dd . 3.2.5 mcu initialization sequence when a reset occurs the stack is reset, the pc is loaded with the address of the reset vector (locat- ed in program rom starting at address 0ffeh). a jump to the beginning of the user program must be coded at this address. following a reset, the in- terrupt flag is automatically set, so that the cpu is in non maskable interrupt mode; this prevents the initialisation routine from being interrupted. the in- itialisation routine should therefore be terminated by a reti instruction, in order to revert to normal mode and enable interrupts. if no pending interrupt is present at the end of the initialisation routine, the mcu will continue by processing the instruction immediately following the reti instruction. if, how- ever, a pending interrupt is present, it will be serv- iced. figure 15. reset and interrupt processing figure 16. reset block diagram reset reset vector jp jp:2 bytes/4 cycles reti reti: 1 byte/2 cycles initialization routine va00181 v dd reset 300k w 2.8k w power watchdog reset ck counter reset st6 intern al reset f osc reset on reset va0200b 127
24/86 st62t32b st62e32b resets (cont'd) table 7. register reset status register address(es) status comment oscillator control register eeprom control register port data registers port direction register port option register interrupt option register timer status/control ar timer status/control 1 register ar timer status/control 2 register ar timer status/control 3 register ar timer status/control 4 register spi registers 0dbh 0dfh 0c0h to 0c2h 0c4h to 0c6h 0cch to 0ceh 0c8h 0d4h 0e8h 0e1h 0e2h oe3h 0dch to 0ddh 00h main oscillator on eeprom enabled i/o are input with or without pull-up depending on port pull option interrupt disabled timer disabled ar timer stopped spi disabled x, y, v, w, register accumulator data ram data ram page register data rom window register eeprom a/d result register ar timer capture register ar timer reload/capture register artimer mask registers artimer compare registers 080h to 083h 0ffh 084h to 0bfh 0cbh 0c9h 00h to 03fh 0d0h 0dbh 0d9h oe0h-oefh oedh-oeeh undefined as written if programmed timer counter register timer prescaler register watchdog counter register a/d control register 0d3h 0d2h 0d8h 0d1h ffh 7fh feh 40h max count loaded a/d in standby uart control uart data register od7h od6h uart disabled 128
25/86 st62t32b st62e32b 3.3 digital watchdog the digital watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. the watchdog circuit generates a reset when the downcounter reaches zero. user software can prevent this reset by reloading the counter, and should therefore be written so that the counter is regularly reloaded while the user program runs correctly. in the event of a software mishap (usual- ly caused by externally generated interference), the user program will no longer behave in its usual fashion and the timer register will thus not be re- loaded periodically. consequently the timer will decrement down to 00h and reset the mcu. in or- der to maximise the effectiveness of the watchdog function, user software must be written with this concept in mind. watchdog behaviour is governed by two options, known as awatchdog activationo (i.e. hardware or software) and aexternal stop mode controlo (see table 8). in the software option, the watchdog is disa- bled until bit c of the dwdr register has been set. when the watchdog is disabled, low power stop mode is available. once activated, the watchdog cannot be disabled, except by resetting the mcu. in the hardware option, the watchdog is per- manently enabled. since the oscillator will run con- tinuously, low power mode is not available. the stop instruction is interpreted as a wait instruc- tion, and the watchdog continues to countdown. however, when the external stop mode control option has been selected low power consumption may be achieved in stop mode. execution of the stop instruction is then gov- erned by a secondary function associated with the nmi pin. if a stop instruction is encountered when the nmi pin is low, it is interpreted as wait, as described above. if, however, the stop in- struction is encountered when the nmi pin is high, the watchdog counter is frozen and the cpu en- ters stop mode. when the mcu exits stop mode (i.e. when an in- terrupt is generated), the watchdog resumes its activity. table 8. recommended option choices functions required recommended optio ns stop mode & watchdog aexternal stop modeo & ahardware watchdogo stop mode asoftwar e watchdogo watchdog ahardware watchdogo 129
26/86 st62t32b st62e32b digital watchdog (cont'd) the watchdog is associated with a data space register (digital watchdog register, dwdr, loca- tion 0d8h) which is described in greater detail in section 3.3.1 digital watchdog register (dwdr) . this register is set to 0feh on reset: bit c is cleared to a0o, which disables the watchdog; the timer downcounter bits, t0 to t5, and the sr bit are all set to a1o, thus selecting the longest watch- dog timer period. this time period can be set to the user's requirements by setting the appropriate val- ue for bits t0 to t5 in the dwdr register. the sr bit must be set to a1o, since it is this bit which gen- erates the reset signal when it changes to a0o; clearing this bit would generate an immediate re- set. it should be noted that the order of the bits in the dwdr register is inverted with respect to the as- sociated bits in the down counter: bit 7 of the dwdr register corresponds, in fact, to t0 and bit 2 to t5. the user should bear in mind the fact that these bits are inverted and shifted with respect to the physical counter bits when writing to this regis- ter. the relationship between the dwdr register bits and the physical implementation of the watch- dog timer downcounter is illustrated in figure 17. only the 6 most significant bits may be used to de- fine the time period, since it is bit 6 which triggers the reset when it changes to a0o. this offers the user a choice of 64 timed periods ranging from 3,072 to 196,608 clock cycles (with an oscillator frequency of 8mhz, this is equivalent to timer peri- ods ranging from 384 m s to 24.576ms). figure 17. watchdog counter control watchdog control register d0 d1 d3 d4 d5 d6 d7 watchdog counter c sr t5 t4 t3 t2 t1 d2 t0 osc 12 reset vr02068a 2 8 130
27/86 st62t32b st62e32b digital watchdog (cont'd) 3.3.1 digital watchdog register (dwdr) address: 0d8h e read/write reset status: 1111 1110b bit 0 = c : watchdog control bit if the hardware option is selected, this bit is forced high and the user cannot change it (the watchdog is always active). when the software option is se- lected, the watchdog function is activated by set- ting bit c to 1, and cannot then be disabled (save by resetting the mcu). when c is kept low the counter can be used as a 7-bit timer. this bit is cleared to a0o on reset. bit 1 = sr : software reset bit this bit triggers a reset when cleared. when c = a0o (watchdog disabled) it is the msb of the 7-bit timer. this bit is set to a1o on reset. bits 2-7 = t5-t0 : downcounter bits it should be noted that the register bits are re- versed and shifted with respect to the physical counter: bit-7 (t0) is the lsb of the watchdog downcounter and bit-2 (t5) is the msb. these bits are set to a1o on reset. 3.3.2 application notes the watchdog plays an important supporting role in the high noise immunity of st62xx devices, and should be used wherever possible. watchdog re- lated options should be selected on the basis of a trade-off between application security and stop mode availability. when stop mode is not required, hardware acti- vation without external stop mode con- trol should be preferred, as it provides maxi- mum security, especially during power-on. when stop mode is required, hardware activa- tion and external stop mode control should be chosen. nmi should be high by default, to allow stop mode to be entered when the mcu is idle. the nmi pin can be connected to an i/o line (see figure 18) to allow its state to be controlled by soft- ware. the i/o line can then be used to keep nmi low while watchdog protection is required, or to avoid noise or key bounce. when no more processing is required, the i/o line is released and the device placed in stop mode for lowest power consumption. when software activation is selected and the watchdog is not activated, the downcounter may be used as a simple 7-bit timer (remember that the bits are in reverse order). the software activation option should be chosen only when the watchdog counter is to be used as a timer. to ensure the watchdog has not been un- expectedly activated, the following instructions should be executed within the first 27 instructions: jrr 0, wd, #+3 ldi wd, 0fdh 70 t0 t1 t2 t3 t4 t5 sr c 131
28/86 st62t32b st62e32b digital watchdog (cont'd) these instructions test the c bit and reset the mcu (i.e. disable the watchdog) if the bit is set (i.e. if the watchdog is active), thus disabling the watchdog. in all modes, a minimum of 28 instructions are ex- ecuted after activation, before the watchdog can generate a reset. consequently, user software should load the watchdog counter within the first 27 instructions following watchdog activation (software mode), or within the first 27 instructions executed following a reset (hardware activation). it should be noted that when the gen bit is low (in- terrupts disabled), the nmi interrupt is active but cannot cause a wake up from stop/wait modes. figure 18. a typical circuit making use of the exernal stop mode control feature figure 19. digital watchdog block diagram i nmi switch i/o vr02002 rsff 8 data bus va00010 -2 -12 oscillator reset write reset db0 r s q db1.7 set load 7 8 -2 set clock 132
29/86 st62t32b st62e32b 3.4 interrupts the cpu can manage four maskable interrupt sources, in addition to a non maskable interrupt source (top priority interrupt). each source is asso- ciated with a specific interrupt vector which con- tains a jump instruction to the associated interrupt service routine. these vectors are located in pro- gram space (see table 9). when an interrupt source generates an interrupt request, and interrupt processing is enabled, the pc register is loaded with the address of the inter- rupt vector (i.e. of the jump instruction), which then causes a jump to the relevant interrupt serv- ice routine, thus servicing the interrupt. interrupt sources are linked to events either on ex- ternal pins, or on chip peripherals. several events can be ored on the same interrupt source, and relevant flags are available to determine which event triggered the interrupt. the non maskable interrupt request has the high- est priority and can interrupt any interrupt routine at any time; the other four interrupts cannot inter- rupt each other. if more than one interrupt request is pending, these are processed by the processor core according to their priority level: source #1 has the higher priority while source #4 the lower. the priority of each interrupt source is fixed. table 9. interrupt vector map 3.4.1 interrupt request all interrupt sources but the non maskable inter- rupt source can be disabled by setting accordingly the gen bit of the interrupt option register (ior). this gen bit also defines if an interrupt source, in- cluding the non maskable interrupt source, can re- start the mcu from stop/wait modes. interrupt request from the non maskable interrupt source #0 is latched by a flip flop which is automat- ically reset by the core at the beginning of the non- maskable interrupt service routine. interrupt request from source #1 can be configu- red either as edge or level sensitive by setting ac- cordingly the les bit of the interrupt option regis- ter (ior). interrupt request from source #2 are always edge sensitive. the edge polarity can be configured by setting accordingly the esb bit of the interrupt op- tion register (ior). interrupt request from sources #3 & #4 are level sensitive. in edge sensitive mode, a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started. so, the occurrence of an interrupt can be stored, until completion of the running interrupt routine be- fore being processed. if several interrupt requests occurs before completion of the running interrupt routine, only the first request is stored. storage of interrupt requests is not available in lev- el sensitive mode. to be taken into account, the low level must be present on the interrupt pin when the mcu samples the line after instruction execu- tion. at the end of every instruction, the mcu tests the interrupt lines: if there is an interrupt request the next instruction is not executed and the appropri- ate interrupt service routine is executed instead. table 10. interrupt option register description interrupt source priority vector address interrupt source #0 1 (ffch-ffdh) interrupt source #1 2 (ff6h-ff7h) interrupt source #2 3 (ff4h-ff5h) interrupt source #3 4 (ff2h-ff3h) interrupt source #4 5 (ff0h-ff1h) gen set enable all interrupts cleared disable all interrupts esb set rising edge mode on inter- rupt source #2 cleared falling edge mode on inter- rupt source #2 les set level-sensitive mode on in- terrupt source #1 cleared falling edge mode on inter- rupt source #1 others not used 133
30/86 st62t32b st62e32b interrupts (cont'd) 3.4.2 interrupt procedure the interrupt procedure is very similar to a call pro- cedure, indeed the user can consider the interrupt as an asynchronous call procedure. as this is an asynchronous event, the user cannot know the context and the time at which it occurred. as a re- sult, the user should save all data space registers which may be used within the interrupt routines. there are separate sets of processor flags for nor- mal, interrupt and non-maskable interrupt modes, which are automatically switched and so do not need to be saved. the following list summarizes the interrupt proce- dure: mcu the interrupt is detected. the c and z flags are replaced by the interrupt flags (or by the nmi flags). the pc contents are stored in the first level of the stack. the normal interrupt lines are inhibited (nmi still active). the first internal latch is cleared. the associated interrupt vectoris loaded inthe pc. warning: in some circumstances, when a maskable interrupt occurs while the st6 core is in normal mode and especially during the execu- tion of an oldi ior, 00ho instruction (disabling all maskable interrupts): if the interrupt arrives during the first 3 cycles of the oldio instruction (which is a 4-cycle instruction) the core will switch to interrupt mode but the flags cn and zn will not switch to the interrupt pair ci and zi. user user selected registers are saved within the in- terrupt service routine (normally on a software stack). the source of the interrupt is found by polling the interrupt flags (if more than one source is associ- ated with the same vector). the interrupt is serviced. return from interrupt (reti) mcu automatically the mcu switches back to the nor- mal flag set (or the interrupt flag set) and pops the previous pc value from the stack. the interrupt routine usually begins by the identify- ing the device which generated the interrupt re- quest (by polling). the user should save the regis- ters which are used within the interrupt routine in a software stack. after the reti instruction is exe- cuted, the mcu returns to the main routine. figure 20. interrupt processing flow chart ins truc tion fetc h ins truct ion exec ute ins tructio n was the ins tructi on areti ? ? c lear int er ru pt mask select pr ogram flags opopo the stack ed pc ? c he ck if the re is an in terr up t re quest an d inte rr upt mask select in tern al mode flag push the pc into the stac k load pc from int err up t vect or (ffc/f fd) set int er ru pt mask no no yes is the c ore alre ady in nor mal mode? va000014 yes no yes 134
31/86 st62t32b st62e32b interrupts (cont'd) 3.4.3 interrupt option register (ior) the interrupt option register (ior) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. this register is write-only and cannot be accessed by single-bit operations. address: 0c8h e write only reset status: 00h bit 7, bits 3-0 = unused . bit 6 = les : level/edge selection bit . when this bit is set to one, the interrupt source #1 is level sensitive. when cleared to zero the edge sensitive mode for interrupt request is selected. bit 5 = esb : edge selection bit . the bit esb selects the polarity of the interrupt source #2. bit 4 = gen : global enable interrupt . when this bit is set to one, all interrupts are enabled. when this bit is cleared to zero all the interrupts (excluding nmi) are disabled. when the gen bit is low, the nmi interrupt is ac- tive but cannot cause a wake up from stop/wait modes. this register is cleared on reset. 3.4.4 iinterrupt sources interrupt sources available on the st62e32b/t32b are summarized in thetable 11 with associated mask bit to enable/disable the in- terrupt request. table 11. interrupt requests and mask bits 70 - les esb gen - - - - peripheral register address register mask bit masked interrupt source interrupt source general ior c8h gen all interrupts, excluding nm i all timer tscr1 d4h eti tmz: timer overflow source 4 a/d converter adcr d1h eai eoc: end of conversion source 4 uart uartcr d7h rxien txien rxrdy : byte received txmt : byte sent source 4 artimer scr1 scr2 scr3 scr3 scr3 e8h e1h e2h e2h e2h ovfien cp1ien cp2ien zeroien cmpien ovfflg: artimer overflow cp1flg cp2flg zeroflg: compare to zero flag cmpflg: compare flag source 3 spi spi dch all end of transmission source 1 port pan orpa-drpa c0h-c4h orpan-drpan pan pin source 1 port pbn orpb-drpb c1h-c5h orpbn-drpbn pbn pin source 2 port pcn orpc-drpc c2h-c6h orpcn-drpcn pcn pin source 0 port pdn orpd-drpd c3h-c7h orpdn-drpdn pdn pin source 2 port pen orpe-drpe fch-fdh orpen-drpen pen pin source 1 135
32/86 st62t32b st62e32b iinterrupts (cont'd) interrupt polarity register (ipr) address: dah e read/write in conjunction with ior register esb bit, the polar- ity of i/o pins triggered interrupts can be selected by setting accordingly the interrupt polarity regis- ter (ipr). if a bit in ipr is set to one the corre- sponding port interrupt is inverted (e.g. ipr bit 2 = 1 ; port c generates interrupt on rising edge. at re- set, ipr is cleared and all port interrupts are not in- verted (e.g. port c generates interrupts on falling edges). bit 7 - bits 5 = unused . bit 4 = port e interrupt polarity . bit 3 = port d interrupt polarity . bit 2 = port c interrupt polarity . bit 1= port a interrupt polarity . bit 0 = port b interrupt polarity . table 12. i/o interrupts selections according to ipr, ior programming 70 - - - porte portd portc porta portb gen ipr3 ipr0 ior5 port b occurence port d occurence interrupt source 1 0 0 0 falling edge falling edge 2 1 0 0 1 rising edge rising edge 1 0 1 0 rising edge falling edge 1 0 1 1 falling edge rising edge 1 1 0 0 falling edge rising edge 1 1 0 1 rising edge falling edge 1 1 1 0 rising edge rising edge 1 1 1 1 falling edge falling edge 0 x x x disabled disabled gen ipr4 ipr1 ior6 port a occurence port e occurence interrupt source 1 0 0 0 falling edge falling edge 1 1 0 0 1 low level low level 1 0 1 0 rising edge falling edge 1 0 1 1 high level low level 1 1 0 0 falling edge rising edge 1 1 0 1 low level high level 1 1 1 0 rising edge rising edge 1 1 1 1 high level high level 0 x x x disabled disabled ipr2 port c occurence interrupt source 0 falling edge 0 1 rising edge 136
33/86 st62t32b st62e32b interrupts (cont'd) figure 21. interrupt block diagram port c port a bits pbe v dd from register port a,b,c,d,e single bit enable ff clk q clr i 0 start restart stop/wa it int #0 nmi (ffc,d)) int #2 (ff4,5) pbe bits nmi port e bits port b bits ipr bit 2 ff clk q clr 0 mux 1 i 1 start pbe ipr bit 0 ipr bit 4 ior bit 6 (les) pbe ipr bit 1 ff clk q clr pbe ipr bit 3 ior bit 5 (esb) i 2 start int #1 (ff6,7) from spi int #3 (ff2,3) int #4 (ff0,1) ior bit 4(gen) port d bits cp1flg cp1ien cp2flg cp2ien ovflg ovfien cmpflg cmpien zeroflg zeroien tmz eti eai eoc rxrdy rxien txmt txien 137
34/86 st62t32b st62e32b 3.5 power saving modes the wait and stop modes have been imple- mented in the st62xx family of mcus in order to reduce the product's electrical consumption during idle periods. these two power saving modes are described in the following paragraphs. 3.5.1 wait mode the mcu goes into wait mode as soon as the wait instruction is executed. the microcontroller can be considered as being in a asoftware frozeno state where the core stops processing the pro- gram instructions, the ram contents and peripher- al registers are preserved as long as the power supply voltage is higher than the ram retention voltage. in this mode the peripherals are still ac- tive. wait mode can be used when the user wants to reduce the mcu power consumption during idle periods, while not losing track of time or the capa- bility of monitoring external events. the active os- cillator is not stopped in order to provide a clock signal to the peripherals. timer counting may be enabled as well as the timer interrupt, before en- tering the wait mode: this allows the wait mode to be exited when a timer interrupt occurs. the same applies to other peripherals which use the clock signal. if the wait mode is exited due to a reset (either by activating the external pin or generated by the watchdog), the mcu enters a normal reset proce- dure. if an interrupt is generated during wait mode, the mcu's behaviour depends on the state of the processor core prior to the wait instruction, but also on the kind of interrupt request which is generated. this is described in the following para- graphs. the processor core does not generate a delay following the occurrence of the interrupt, be- cause the oscillator clock is still available and no stabilisation period is necessary. 3.5.2 stop mode if the watchdog is disabled, stop mode is availa- ble. when in stop mode, the mcu is placed in the lowest power consumption mode. in this oper- ating mode, the microcontroller can be considered as being afrozeno, no instruction is executed, the oscillator is stopped, the ram contents and pe- ripheral registers are preserved as long as the power supply voltage is higher than the ram re- tention voltage, and the st62xx core waits for the occurrence of an external interrupt request or a reset to exit the stop state. if the stop state is exited due to a reset (by acti- vating the external pin) the mcu will enter a nor- mal reset procedure. behaviour in response to in- terrupts depends on the state of the processor core prior to issuing the stop instruction, and also on the kind of interrupt request that is gener- ated. this case will be described in the following para- graphs. the processor core generates a delay af- ter occurrence of the interrupt request, in order to wait for complete stabilisation of the oscillator, be- fore executing the first instruction. 138
35/86 st62t32b st62e32b power saving mode (cont'd) 3.5.3 exit from wait and stop modes the following paragraphs describe how the mcu exits from wait and stop modes, when an inter- rupt occurs (not a reset). it should be noted that the restart sequence depends on the original state of the mcu (normal, interrupt or non-maskable in- terrupt mode) prior to entering wait or stop mode, as well as on the interrupt type. interrupts do not affect the oscillator selection. 3.5.3.1 normal mode if the mcu was in the main routine when the wait or stop instruction was executed, exit from stop or wait mode will occur as soon as an interrupt oc- curs; the related interrupt routine is executed and, on completion, the instruction which follows the stop or wait instruction is then executed, pro- viding no other interrupts are pending. 3.5.3.2 non maskable interrupt mode if the stop or wait instruction has been execut- ed during execution of the non-maskable interrupt routine, the mcu exits from the stop or wait mode as soon as an interrupt occurs: the instruction which follows the stop or wait instruction is ex- ecuted, and the mcu remains in non-maskable in- terrupt mode, even if another interrupt has been generated. 3.5.3.3 normal interrupt mode if the mcu was in interrupt mode before the stop or wait instruction was executed, it exits from stop or wait mode as soon as an interrupt oc- curs. nevertheless, two cases must be consid- ered: if the interrupt is a normal one, the interrupt rou- tine in which the wait or stop mode was en- tered will be completed, starting with the execution of the instruction which follows the stop or the wait instruction, and the mcu is still in the interrupt mode. at the end of this rou- tine pending interrupts will be serviced in accord- ance with their priority. in the event of a non-maskable interrupt, the non-maskable interrupt service routine is proc- essed first, then the routine in which the wait or stop mode was entered will be completed by executing the instruction following the stop or wait instruction. the mcu remains in normal interrupt mode. notes: to achieve the lowest power consumption during run or wait modes, the user program must take care of: configuring unused i/os as inputs without pull-up (these should be externally tied to well defined logic levels); placing all peripherals in their power down modes before entering stop mode; when the hardware activated watchdog is select- ed, or when the software watchdog is enabled, the stop instruction is disabled and a wait instruc- tion will be executed in its place. if all interrupt sources are disabled (gen low), the mcu can only be restarted by a reset. although setting gen low does not mask the nmi as an in- terrupt, it will stop it generating a wake-up signal. the wait and stop instructions are not execut- ed if an enabled interrupt request is pending. 139
36/86 st62t32b st62e32b 4 on-chip peripherals 4.1 i/o ports the mcu features input/output lines which may be individually programmed as any of the following input or output configurations: input without pull-up or interrupt input with pull-up and interrupt input with pull-up, but without interrupt analog input push-pull output open drain output the lines are organised as bytewise ports. each port is associated with 3 registers in data space. each bit of these registers is associated with a particular line (for instance, bits 0 of port a data, direction and option registers are associat- ed with the pa0 line of port a). the data registers (drx), are used to read the voltage level values of the lines which have been configured as inputs, or to write the logic value of the signal to be output on the lines configured as outputs. the port data registers can be read to get the effective logic levels of the pins, but they can be also written by user software, in conjunction with the related option registers, to select the dif- ferent input mode options. single-bit operations on i/o registers are possible but care is necessary because reading in input mode is done from i/o pins while writing will direct- ly affect the port data register causing an unde- sired change of the input configuration. the data direction registers (ddrx) allow the data direction (input or output) of each pin to be set. the option registers (orx) are used to select the different port options available both in input and in output mode. all i/o registers can be read or written to just as any other ram location in data space, so no extra ram cells are needed for port data storage and manipulation. during mcu initialization, all i/o reg- isters are cleared and the input mode with pull-ups and no interrupt generation is selected for all the pins, thus avoiding pin conflicts. figure 22. i/o port block diagram v dd reset s in controls s out shift register data data direction register register option register input/outp ut to inte rrupt v dd to adc va00413 140
37/86 st62t32b st62e32b i/o ports (cont'd) 4.1.1 operating modes each pin may be individually programmed as input or output with various configurations. this is achieved by writing the relevant bit in the data (dr), data direction (ddr) and option reg- isters (or). table 13 illustrates the various port configurations which can be selected by user soft- ware. 4.1.1.1 input options pull-up, high impedance option. all input lines can be individually programmed with or without an internal pull-up by programming the or and dr registers accordingly. if the pull-up option is not selected, the input pin will be in the high-imped- ance state. 4.1.1.2 interrupt options all input lines can be individually connected by software to the interrupt system by programming the or and dr registers accordingly. the inter- rupt trigger modes (falling edge, rising edge and low level) can be configured by software as de- scribed in the interrupt chapter for each port. 4.1.1.3 analog input options some pins can be configured as analog inputs by programming the or and dr registers according- ly. these analog inputs are connected to the on- chip 8-bit analog to digital converter. only one pin should be programmed as an analog input at any time, since by selecting more than one input simultaneously their pins will be effectively short- ed. table 13. i/o port option selection note: x = don't care ddr or dr mode option 0 0 0 input with pull-up, no interrupt 0 0 1 input no pull-up, no interrupt 0 1 0 input with pull-up and with interrupt 0 1 1 input analog input (when available) 1 0 x output open-drain output (20ma sink when available) 1 1 x output push-pull output (20ma sink when available) 141
38/86 st62t32b st62e32b i/o ports (cont'd) 4.1.2 safe i/o state switching sequence switching the i/o ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. the recom- mended safe transitions are illustrated in figure 23. all other transitions are potentially risky and should be avoided when changing the i/o operat- ing mode, as it is most likely that undesirable side- effects will be experienced, such as spurious inter- rupt generation or two pins shorted together by the analog multiplexer. single bit instructions (set, res, inc and dec) should be used with great caution on ports data registers, since these instructions make an implicit read and write back of the entire register. in port input mode, however, the data register reads from the input pins directly, and not from the data regis- ter latches. since data register information in input mode is used to set the characteristics of the input pin (interrupt, pull-up, analog input), these may be unintentionally reprogrammed depending on the state of the input pins. as a general rule, it is better to limit the use of single bit instructions on data registers to when the whole (8-bit) port is in output mode. in the case of inputs or of mixed inputs and outputs, it is advisable to keep a copy of the data register in ram. single bit instructions may then be used on the ram copy, after which the whole copy register can be written to the port data regis- ter: set bit, datacopy ld a, datacopy ld dra, a warning: care must also be taken to not use in- structions that act on a whole port register (inc, dec, or read operations) when all 8 bits are not available on the device. unavailable bits must be masked by software (and instruction). the wait and stop instructions allow the st62xx to be used in situations where low power consumption is needed. the lowest power con- sumption is achieved by configuring i/os in input mode with well-defined logic levels. the user must take care not to switch outputs with heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to the conversion. figure 23. diagram showing safe i/o state transitions note *. xxx = ddr, or, dr bits respectively interrupt pull-up output open drain output push-pull input pull-up (reset state) input analog output open drain output push-pull input 010* 000 100 110 011 001 101 111 142
39/86 st62t32b st62e32b i/o ports (cont'd) table 14. i/o port configuration for the st62t32b/e32b note 1 . provided the correct configuration has been selected. mode available on (1) schematic input (reset state if port pull option disabled) pa0-pa7 pb0, pb3-pb7 pc5-pc7 pd0-pd7 pe0-pe4 input with pull up (reset state if port pull option enabled) pa0-pa7 pb0, pb3-pb7 pc5-pc7 pd0-pd7 pe0-pe4 input with pull up with interrupt pa0-pa7 pb0, pb3-pb7 pc5-pc7 pd0-pd7 pe0-pe4 analog input pa4-pa7 pb0, pb3-pb7 pc5-pc7 pd0-pd7 open drain output 5ma open drain output 20ma pa4-pa7 pb0, pb3-pb7 pc5-pc7 pd0-pd7 pa0-pa3 pe0-pe4 push-pull output 5ma push-pull output 20ma pa4-pa7 pb0, pb3-pb7 pc5-pc7 pd0-pd7 pa0-pa3 pe0-pe4 data in interrupt data in interrupt data in interrupt data out adc data out vr01992a 143
40/86 st62t32b st62e32b i/o ports (cont'd) 4.1.3 artimer alternate functions as long as pwmen (resp. ovfen) bit is kept low, the pa3/pwm (resp. pa2/ovf) pin is used as standard i/o pin and therefore can be configured in any mode through the ddr and or registers. if pwmen (resp. ovfen) bit is set, pa3/pwm (re- sp. pa2/ovf) pin must be configured as output through the ddr and or registers to be used as pwm (ovf) output of the artimer16. all output modes are available. pa4/cp1 or pa5/cp2 pins must be configured as input through ddr register to allow cp1 or cp2 triggered input capture of the artimer16. all input modes are available and i/o's can be read inde- pendantly of the artimer at any time. as long as rldsel2, rldsel1 bits do not enable cp1 or cp2 triggered capture, pa4/cp1 and pa5/cp2 are standard i/o's configurable through ddr and or registers. 4.1.4 spi alternate functions pd2/sin and pd1/scl pins must be configured as input through the ddr and or registers to be used as data in and data clock (slave mode) for the spi. all input modes are available and i/o's can be read independantly of the spi at any time. pd3/sout must be configured in open drain output mode to be used as data out for the spi. in output mode, the value present on the pin is the port data register content only if pd3 is defined as push pull output, while serial transmission is possible only in open drain mode. 4.1.5 uart alternate functions pd4/rxd1 pin must be configured as input through the ddr and or registers to be used as reception line for the uart. all input modes are available and pd4 can be read independantly of the uart at any time. pd5/txd1 pin must be configured as output through the ddr and or registers to be used as transmission line for the uart. value present on the pin in output mode is the data register content as long as no transmission is active. 144
41/86 st62t32b st62e32b i/o ports (cont'd) figure 24. peripheral interface configuration of spi, uart and ar timer16 pd4/rxd1 pid 0 mux 1 pd5/txd1 pd3/sout pd2/sin pd1/scl pa3/pwm pa4/cp1 pa5/cp2 pa2/ovf v dd dr rxd uart iartoe txd pid dr pid opr dr 1 mux 0 out in synchronous serial i/o clock pid dr pid dr pp/od pid dr 1 mux 0 pwmen pwm cp1 artimer 16 cp2 ovfen ovf pid dr pid dr pid dr 1 mux 0 vr01661d 145
42/86 st62t32b st62e32b i/o ports (cont'd) 4.1.6 i/o port option registers ora/b/c/d/e (cch pa, cdh pb, ceh pc, cfh pd, feh pe) read/write bit 7-0 = px7 - px0 : port a, b, c, d and e option register bits. 4.1.7 i/o port data direction registers ddra/b/c/d/e (c4h pa, c5h pb, c6h pc, c7h pd, fdh pe) read/write bit 7-0 = px7 - px0 : port a, b, c, d and e data di- rection registers bits. 4.1.8 i/o port data registers dra/b/c/d/e (c0h pa, c1h pb, c2h pc, c3h pd, fch pe) read/write bit 7-0 = px7 - px0 : port a, b, c, d and e data registers bits. 70 px7 px6 px5 px4 px3 px2 px1 px0 70 px7 px6 px5 px4 px3 px2 px1 px0 70 px7 px6 px5 px4 px3 px2 px1 px0 146
43/86 st62t32b st62e32b 4.2 timer the mcu features an on-chip timer peripheral, consisting of an 8-bit counter with a 7-bit program- mable prescaler, giving a maximum count of 2 15 . the peripheral may be configured in three different operating modes. figure 25 shows the timer block diagram. the external timer pin is available to the user. the content of the 8-bit counter can be read/written in the timer/counter register, tcr, while the state of the 7-bit prescaler can be read in the psc register. the control logic device is managed in the tscr register as described in the following paragraphs. the 8-bit counter is decremented by the output (rising edge) coming from the 7-bit prescaler and can be loaded and read under program control. when it decrements to zero then the tmz (timer zero) bit in the tscr is set to a1o. if the eti (ena- ble timer interrupt) bit in the tscr is also set to a1o, an interrupt request is generated as described in the interrupt chapter. the timer interrupt can be used to exit the mcu from wait mode. the prescaler input can be the internal frequency f int divided by 12 or an external clock applied to the timer pin. the prescaler decrements on the rising edge. depending on the division factor pro- grammed by ps2, ps1 and ps0 bits in the tscr. the clock input of the timer/counter register is mul- tiplexed to different sources. for division factor 1, the clock input of the prescaler is also that of tim- er/counter; for factor 2, bit 0 of the prescaler regis- ter is connected to the clock input of tcr. this bit changes its state at half the frequency of the pres- caler input clock. for factor 4, bit 1 of the psc is connected to the clock input of tcr, and so forth. the prescaler initialize bit, psi, in the tscr regis- ter must be set to a1o to allow the prescaler (and hence the counter) to start. if it is cleared to a0o, all the prescaler bits are set to a1o and the counter is inhibited from counting. the prescaler can be loaded with any value between 0 and 7fh, if bit psi is set to a1o. the prescaler tap is selected by means of the ps2/ps1/ps0 bits in the control reg- ister. figure 26 illustrates the timer's working principle. figure 25. timer block diagram databus 8 8 8 8 8-bit counter 6 5 4 3 2 1 0 psc status/control register b7 b6 b 5 b4 b3 b 2 b 1 b0 tmz et i to ut dout psi ps2 ps1 ps0 select 1of7 3 latch synchronization logic timer interrupt line va00009 :12 f osc 147
44/86 st62t32b st62e32b timer (cont'd) 4.2.1 timer operating modes there are three operating modes, which are se- lected by the tout and dout bits (see tscr register). these three modes correspond to the two clocks which can be connected to the 7-bit prescaler (f int 12 or timer pin signal), and to the output mode. 4.2.1.1 gated mode (tout = a0o, dout = a1o) in this mode the prescaler is decremented by the timer clock input (f int 12), but only when the signal on the timer pin is held high (allowing pulse width measurement). this mode is selected by clearing the tout bit in the tscr register to a0o (i.e. as input) and setting the dout bit to a1o. 4.2.1.2 event counter mode (tout = a0o, dout = a0o) in this mode, the timer pin is the input clock of the prescaler which is decremented on the rising edge. 4.2.1.3 output mode (tout = a1o, dout = data out) the timer pin is connected to the dout latch, hence the timer prescaler is clocked by the pres- caler clock input (f int 12). the user can select the desired prescaler division ratio through the ps2, ps1, ps0 bits. when the tcr count reaches 0, it sets the tmz bit in the tscr. the tmz bit can be tested under program control to perform a timer function whenever it goes high. the low-to-high tmz bit transition is used to latch the dout bit of the tscr and trans- fer it to the timer pin. this operating mode allows external signal generation on the timer pin. table 15. timer operating modes 4.2.2 timer interrupt when the counter register decrements to zero with the eti (enable timer interrupt) bit set to one, an interrupt request is generated as described in the interrupt chapter. when the counter decrements to zero, the tmz bit in the tscr register is set to one. figure 26. timer working principle tout dout timer pin timer function 0 0 input event counter 0 1 input gated input 1 0 output output a0o 1 1 output output a1o bit0 bit1 bit2 bit3 bit6 bit5 bit4 clock 7-bit prescaler 8-1 multiplexer 8-bit counter bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 0 2 34 56 7 ps0 ps1 ps2 va00186 148
45/86 st62t32b st62e32b timer (cont'd) 4.2.3 application notes the user can select the presence of an on-chip pull-up on the timer pin as option. tmz is set when the counter reaches zero; howev- er, it may also be set by writing 00h in the tcr register or by setting bit 7 of the tscr register. the tmz bit must be cleared by user software when servicing the timer interrupt to avoid unde- sired interrupts when leaving the interrupt service routine. after reset, the 8-bit counter register is loaded with 0ffh, while the 7-bit prescaler is load- ed with 07fh, and the tscr register is cleared. this means that the timer is stopped (psi=a0o) and the timer interrupt is disabled. if the timer is programmed in output mode, the dout bit is transferred to the timer pin when tmz is set to one (by software or due to counter decrement). when tmz is high, the latch is trans- parent and dout is copied to the timer pin. when tmz goes low, dout is latched. a write to the tcr register will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a tcr register decrement to 00h occur simultaneously, the write will take precedence, and the tmz bit is not set until the 8-bit counter reaches 00h again. the values of the tcr and the psc registers can be read accurately at any time. 4.2.4 timer registers timer status control register (tscr) address: 0d4h e read/write bit 7 = tmz : timer zero bit a low-to-high transition indicates that the timer count register has decrement to zero. this bit must be cleared by user software before starting a new count. bit 6 = eti : enable timer interrupt when set, enables the timer interrupt request. if eti=0 the timer interrupt is disabled. if eti=1 and tmz=1 an interrupt request is generated. bit 5 = tout : timers output control when low, this bit selects the input mode for the timer pin. when high the output mode is select- ed. bit 4 = dout : data output data sent to the timer output when tmz is set high (output mode only). input mode selection (input mode only). bit 3 = psi : prescaler initialize bit used to initialize the prescaler and inhibit its count- ing. when psi=a0o the prescaler is set to 7fh and the counter is inhibited. when psi=a1o the prescal- er is enabled to count downwards. as long as psi=a0o both counter and prescaler are not run- ning. bit 2, 1, 0 = ps2, ps1, ps0 : prescaler mux. se- lect. these bits select the division ratio of the pres- caler register. table 16. prescaler division factors timer counter register tcr address: 0d3h e read/write bit 7-0 = d7-d0 : counter bits. prescaler register psc address: 0d2h e read/write bit 7 = d7 : always read as o0o. bit 6-0 = d6-d0 : prescaler bits. 70 tmz eti tout dout psi ps2 ps1 ps0 ps2 ps1 ps0 divided by 0001 0012 0104 0118 10016 10132 11064 1 1 1 128 70 d7 d6 d5 d4 d3 d2 d1 d0 70 d7 d6 d5 d4 d3 d2 d1 d0 149
46/86 st62t32b st62e32b 4.3 artimer 16 the artimer16 is a timer module based on a 16 bit downcounter with reload, capture and com- pare features to manage timing requirements. two outputs provide pwm and overflow (ovf) output signals each with programmable polarity, and two inputs cp1 and cp2 control start-up, capture and/or reload operations on the central counter. the artimer16 includes four 16-bit registers cmp,rlcp,mask and cp for the reload, cap- ture and compare functions, four 8-bit status/con- trol registers and the associated control logic.the 16-bit registers are accessed from the 8-bit inter- nal bus. the full 16-bit word is written in two bytes, the high byte first and then the low byte. the high byte is stored in an intermediate register and is written to the target 16-bit register at the same time as the write to the low byte. this high byte will remain constant if further writes are made to the low bytes, until the high byte is changed. full read/write access is available to all registers ex- cept where mentioned. the artimer16 may be placed into the reset mode by resetting runres to 0 in order to achieve lower consumption. the contents of rlcp, cp, mask and cmp are not affected, nor is the previous run mode of the timer changed. if runres is subsequently set to 1, the timer re- starts in the same run mode as previously set if no changes are made to the timer status registers. finally, interrupt capabilities are associated to the reload, capture and compare features. figure 27. artimer16 block diagram scr1 scr2 scr3 scr4 bus interface 8-bit mcu data bus 16-bit data bus 8 8 8 4 8 16 16 16 cmp mask rlcp cp 16 16 counter control logic compare-to-0 compare psc f int pwm ovf cp1 cp2 int 16-bit 16-bit 16-bit 16-bit vr02014 150
47/86 st62t32b st62e32b 4.3.1 central counter the core of the 16 bit auto-reload timer is a 16- bit synchronous downcounter which accepts the mcu internal clock through a prescaler with a pro- grammable ratio (1/1, 1/4, 1/16). the maximum time for downcounting is therefore 2 16 x psc x tclk where psc is the prescaler ratio, and tclk the period of the main oscillator. this down counter is stopped and its content kept cleared as long as runres bit is cleared. 4.3.1.1 reload functions the 16-bit down counter can be reloaded 3 differ- ent ways: at a zero overflow occurrence with the bit reload cleared: the counter is reloaded to ffffh. at a zero overflow occurrence with the bit reload set: the counter is reloaded with the val- ue programmed in the rlcp register. for each overflow, the transition between 0000h and the re- load value (rlcp or ffffh) is flagged through the ovfflg bit. at an external event on pin cp1 or cp2 with the bit reload set: the counter is reloaded with the val- ue programmed in the rlcp register. as a consequence, the time between a timer re- load and a zero overflow occurrence depends on the value in rlcp when reload bit is set. this time is equal to (rlcp+1) x psc x tclk when reload bit is set, while it is 2 16 x psc x tclk when reload bit is cleared. 4.3.1.2 compare functions the value in the counter ct is continuously com- pared to 0000h and to the value programmed into the compare register cmp. the comparison range to 0000h and cmp is defined by using the mask register to select which bits are used, there- fore the comparisons performed are: mask&ct = ? mask&cmp. mask&ct = ? 0000h. when a matched comparison to 0000h or mask&cmp occurs, the flags zeroflg and compflg are respectively set. by using mask values reported in table 17, the mask register works as counter frequency multi- plier for the compare functions. in that case posi- tive masked comparison occur with a period of 2 (n+1) x psc x tclk where n is the position of the most significant bit of mask value. table 17. recommended mask values note : writing 0000h in mask gives a period equal to two times the prescaled period psc x tclk. figure 28. flags setting in compare and reload functions hexadecimal binary msbit at 1 position,n ffffh 7fffh 3fffh 1fffh 0fffh ... 0007h 0003h 0001h 1111 1111 1111 1111 0111 1111 1111 1111 0011 1111 1111 1111 0001 1111 1111 1111 0000 1111 1111 1111 ... 0000 0000 0000 0111 0000 0000 0000 0011 0000 0000 0000 0001 15 14 13 12 11 2 1 0 cmp counter zeroflg 0 ffffh or rlcp software reset software reset software reset ovfflg compflg value ct 151
48/86 st62t32b st62e32b central counter (cont'd) 4.3.1.3 capture functions content of the counter ct can always be down- loaded (captured) into the cp register at selecta- ble event occurrence on pins cp1 and cp2, while capture in rlcp is possible only when the bit reload is cleared. capture functions with reload cleared are used for period or pulse width measurements with input cp2, or for phase measurements between two signals on cp1 and cp2, with the counter in free running mode. in these modes, counter values by the two events occurence are stored into rlcp and cp and the counter remains in free running mode. capture functions with reload set, are used for same application purpose, but in that case, the first event reloads the counter from rlcp while the second event captures the counter content into the cp register. therefore, the counter is not in free running mode for other functions since the down counting start is initiated by either cp1, cp2 or runres event according to rldsel1 and rldsel2 bit. 4.3.2 signal generation modes 4.3.2.1 output modes any positive comparison to 0000h or mask&cmp, and any overflow occurence can be used to control the ovf or pwm output pins in various modes defined by bits ovfmd, pwmpol, pwmen and pwmmd. pwm pin output modes ovf pin output modes * the ovf pin is reset by clearing the flag ovf- flg. 4.3.2.2 frequency and duty cycles on pwm pins in set/reset mode (pwmmd=0), the period on the pwm pin is the time between two matched masked comparison to 0000h, at which pwm pin is set (pwmpol=1) or reset (pwmpol=0). as long as no reload function from rlcp is performed (reload bit cleared) and no mask is used, this value is 2 16 x psc x tclk. if, on the contrary, reload function or a mask are used, the frequency is con- trolled through the rlcp and mask values (fig- ure 29). the condition to reset (pwmpol=1) or set back (pwmpol=0) pwm pin is a matched masked comparison to cmp. given a rlcp and mask values within the table 17, cmp defines the duty cycle. in toggle mode (pwmmd=1), pwm pin changes of state at each positive masked comparison to cmp value. the frequency is half the frequency in set/reset mode and the duty-cycle is always 50%. 4.3.2.3 frequency and duty cycles on ovf pin ovf pin activation is directed by the timer overflow occurence and therefore its frequency depends only of the downcounting time from the reload val- ue to 0000h. this means its period is equal to t= (rlcp+1) x psc x tclk in set/reset mode and 2 x (rlcp+1) x psc x tclk in toggle mode. duty cycle is controlled in set/reset mode (ovfmd cleared) by software, since ovf pin can be reset only by clearing the ovfflg bit. in toggle mode (ovfmd set), the duty cycle is always 50%. table 18. achievable periods on pwm pin note : n is the position of the most significant bit of mask value. mask & cnt = 0000h x x no yes no yes x mask&ct= mask&cmp x x yes no yes no yes pwmen 0 0 1 1 1 1 1 pwmmd x x 0 0 0 0 1 pwmpol 0 1 0 0 1 1 x pwm pin 0 1 reset set set reset toggle zero overflow (ovfflg) 1 1 ovfmd 0 1 ovf pin set* toggle mask value ffffh xxxxh period in set/reset mode (pwmmd=0) (rlcp+1) x psc x tclk 2 (n+1) x psc x tclk period in toggle mode (pwmmd=1) 2 x (rlcp+1) x psc x tclk 2 x 2 (n+1) x psc x tclk 152
49/86 st62t32b st62e32b figure 29. mask impact on the compare functions in pwm mode (pwmd=0, pwmpol=1) fedcba987 65432 10f mask 000fh 0007h 0003h 0001h cmp = 000fh counter 2 4 /f clk most significant a1o is bit 3 2 3 /f clk a1o is bit 2 2 2 /f clk a1o is bit 1 2 1 /f clk a1o is bit 0 most most most 0003&000c = 0000h 0003&0007 = 0003&000f significant significant significant bit 0...3 153
50/86 st62t32b st62e32b 4.3.3 timings measurement modes these modes are based on the capture of the down counter content into either cp or rlcp reg- isters. some are used in conjunction with a syn- chronisation of the down counter by reload func- tions on external event on cpi pins or software runres setting, while other modes do not affect the downcounting. as long as reload bit is cleared, the down counter remains in free running mode. 4.3.3.1 timing measurement with startup control three startup conditions, selected by rldseli bit can reload the counter from rlcp and initiate the down counting when reload bit is set. the first mode is software controlled through the runres bit, while the two others are based on external event on pins cp1 and cp2 with configurable polarities. external event on cp2 pin (with configurable po- larities) is used as strobe to launch the capture of the ct counter into cp. when reload bit is set, rlcp cannot be used for capture, since it contains the reload value.. finally, 3 different reload/capture sequences are available: cp1 triggered restart mode with cp2 event de- tection. cp2 triggered restart mode with second cp2 event detection. software triggered restart mode with cp2 event detection. cp1 triggered restart mode with cp2 event de- tection . this mode is enabled for rldsel2=0 and rldsel1=1. external events on cpi pins are enabled as soon as runres bit is set, which lets the prescaler and the down counter running. the next active edge on cp1 causes the counter to be loaded from rlcp, the cp1flg to be set and the downcounting starts from rlcp value. each following active edge on cp1 will cause a reload of the counter. if cp1flg is not reset before the next reload, the cp1err flag is set at the same time as the counter is reloaded. both flags should then be cleared by software. while the counter is counting, any active edge on cp2 will capture the value of the counter at that in- stant into the cp register and set the cp2flg bit. if cp2flg is not cleared before the following cp2 event, the cp2err flag bit is set, and no new cap- ture can be performed capturing is re-enabled by clearing both cp2flg and cp2err. if a capture on cp2 and a reload on cp1 occur at the same time, the capture of the counter to cp is made first, and then the counter is reloaded from rlcp. figure 30. cp1 triggered restart mode with cp2 event detection reload 1 reload on cp1,cp2, runres / capture cp2 0 capture cp1 / capture cp2 vr02007 counter cp1 set cp1flg set cp1err 0000h 0000h ct disabled enable the inputs runres software reset reload and start reload reload set cp1flg disabled set cp2err disabled capture ct into cp set cp2flg cp2 disabled first capture in cp then reload set cp1err, cp2flg clear all flags 154
51/86 st62t32b st62e32b timings measurement modes (cont'd) cp2 triggered restart mode with cp2 event de- tection. this mode is enabled for rldsel2=1 and rldsel1=0. as long as runres bit is set, an external event on cp2 pin generates both, at first the capture into cp, and then the reload from rlcp. capture into cp on cp2 event is enabled only if cp2flg and cp2err are cleared, otherwise only reload func- tions from rlcp are performed. an external event on cp1 activates cp1flg or cp1err flags without any impact on the reload or capture functions. note : after reset, the first cp2 event will capture the 0000h state of the counter into cp and then will restart the counter after loading it from rlcp. cp2flg flag must always be cleared to execute another capture into cp. software triggered restart mode with cp2 event detection. this mode is enabled for rldsel2=0 and rldsel1=0. runres bit setting initiates the reload and startup of the downcounting, while cp2 is used as strobe source for the ct capture into cp register. figure 31. cp2 triggered restart mode with cp2 event detection figure 32. software triggered restart mode with cp2 event detection vr02007c cp1 no action set cp2err first capture ct into cp cp2 set cp1err set cp1flg reload ct from rlcp then reload ct from rlcp set cp2flg reload ct from rlcp vr02007d counter cp1 cp1 disabled 0000h 0000h ct load counter from rlcp and startup runres software reset set cp1flg cp2 disabled cp2 set cp2err cp1 disabled set cp1err capture ct into cp set cp2flg 155
52/86 st62t32b st62e32b timings measurement modes (cont'd) 4.3.3.2 timing measurement without startup control the down counter is in free running mode with runres bit set and reload bit cleared. this means counter automatically restarts from ffffh on zero overflow and signal generation on pwm and ovf pins is not affected. two independent capture paths exist to cp and rlcp, which are both read only registers. cp1 is the source (configurable polarity) for a capture into rlcp while cp2 is the source (configurable polarity) of a capture into cp. independently of cp2 signal, if cp1flg and cp1err are cleared, the first active edge on cp1 will trigger a capture into rlcp, triggering cp1flg. as long as cp1flg has not been cleared, a second following active edge will trig cp1err without any capture into neither rlcp nor cp. independently of cp1 signal, if cp2flg and cp2err are cleared, the first active edge on cp2 will trigger a capture into cp, triggering cp2flg. as long as cp2flg has not been cleared, a sec- ond following active edge will trig cp2err without any capture into neither rlcp or cp. 4.3.4 interrupt capabilities the interrupt source latches of the artimer16 are always enabled and set any time the interrupt condition occurs. the interrupt output is a logical or of five logical ands: int = [(cp1flg & cp1ien) or (cp2flg & cp2ien) or(ovfflg & ovfien) or(compflg & cmpien) or (zeroflg & zeroien)] thus, if any enable bit is 1, the interrupt output of the artimer16 goes high when the respective flag is set. if no enable bit is 1, and one of the in- terrupt flags is set, the interrupt output remains 0, but if the respective enable bit is set to 1 through a write operation, the interrupt output will go high, signalling the interrupt to the core. figure 33. positive cp1 - to negative cp2-edge measurement ( cp1pol = 1, cp2pol = 0) application note: depending on polarity setting for cp1/cp2, and of cp1/cp2 connections, phase, period and pulse width measurements can be achieved. the total independence between cp1 and cp2 captures al- lows phase detection by measuring which of cp1flg or cp2flg is set at first following a reset of these flags. vr02006f counter cp1 cp2 capture into rlcp set cp1flg set cp1err set cp2flg capture into cp set cp2err cp1=cp2 cp1pol=cp2pol measurement yes yes period yes no pulse width no x phase 156
53/86 st62t32b st62e32b 4.3.5 control registers status control register 1 (scr1) address: e8h - read/write/clear only bits 7 & 6 = psc2..psc1 . clock prescaler . these bits define the prescaler options for the prescaler to the counter register according to the following table. the prescaler must be disabled (psc2 = 0, psc1 = 0) before a new prescaler factor is set if the counter is running (after a hardware reset the prescaler is automatically disabled). to avoid inconsistencies in timing, the prescaler factor should be set first, and then the counter started. bit 5 = reload . reload enabled. when set this bit enables reload from rlcp register into ct reg- ister. on the contrary, if reload is cleared, rlcp is used as target for capture from the coun- ter ct register. bit 4 = runres . run/reset . this bit enables the run or reset operation of the artimer. if 0, the counter ct is cleared to zero, and is stopped. setting this bit to 1 permits the startup of the counter, and enables the synchronisation cir- cuits for the timer inputs cp1 and cp2. bit 3 = ovfien . overflow int. enable . the over- flow interrupt is masked when this bit is 0. setting the bit to 1 enables the overflow flag to set the artimer interrupt. bit 2 = ovfflg . when this bit is 0, no overflow has occurred since the last clear of this bit. if the bit is at 1, an overflow has occurred. this bit cannot be set by program, only cleared. bit 1 = ovfmd . the overflow output mode is set by this bit; when 0, the overflow output is run in set mode (ovf will be set on the first overflow event, and will be reset when ovfflg is cleared). when 1 the overflow output is in toggle mode; ovf tog- gles its state on every overflow event (independ- ent to the state of ovfflg). bit 0 = this bit is reserved and must be set to 0. status control register 2 (scr2) address: e1h - read/write/clear only bit 7 = reserved. must be kept cleared. bit 6 = cp1err . cp1 error flag . this bit is set to 1 if a new cp1 event has taken place since cp1flg was set to signal an error condition, it is 0 if there has been no event. it is recommended to clear cp1err at any time that cp1flg is cleared, as further cp1 events cannot be recognised if cp1err is set. this bit cannot bet set by write, only cleared. bit 5 = cp2err . cp1 error flag . this bit is set to 1 if a new cp2 event has taken place since cp2flg was set to signal an error condition, it is 0 if there has been no event. it is recommended to clear cp2err at any time that cp2flg is cleared, as further cp2 events cannot be recognised if cp2err is set. this bit cannot bet set by write, only cleared. bit 4 = cp1ien . cp1 interrupt enable .cp1the capture 1 interrupt is masked when this bit is 0. setting the bit to 1 enables the cp1 event flag cp1flg to set the artimer interrupt. bit 3 = cp1flg . cp1 interrupt flag . when this bit is 0, no cp1 event has occurred since the last clear of this bit. if the bit is at 1, a cp1 event has occurred. this bit cannot be set by program, only cleared. bit 2 = cp1pol . cp1 edge polarity select . cp1pol defines the polarity for triggering the cp1 event. a 0 defines the action on a falling edge on the cp1 input, a 1 on a rising edge. bit 1 & 0 = rldsel2..rldsel1 . reload source select . these bits define the source for the reload events; they do not affect the operation of the cap- ture modes. 70 psc2 psc1 reload runres ovfien ovfflg ovfmd - psc2 psc1 function 00 clock disabled (prescaler and counter stopped 0 1 prescale by 1 1 0 prescale by 4 1 1 prescale by 16 70 - cp1err cp2err cp1ien cp1flg cp1pol rldsel2 rldsel1 rldsel2 rldsel1 function 00 reload and startup triggered by runres 01 reload triggered by every cp1 event 10 reload triggered by every cp2 event 1 1 reload disabled 157
54/86 st62t32b st62e32b control registers (cont'd) status control register 3 (scr3) address: e2h - read/write/clear only bit 7 = cp2pol . cp2 edge polarity select . cp2pol defines the polarity for triggering the cp2 event. a 0 defines the action on a falling edge on the cp2 input, a 1 on a rising edge. bit 6 = cp2ien . cp2 interrupt enable . the cap- ture 2 interrupt is masked when this bit is 0. set- ting the bit to 1 enables the cp2 event flag cp2flg to set the artimer interrupt. bit 5 = cp2flg . cp2 interrupt flag . when this bit is 0, no cp2 event has occurred since the last clear of this flag. if the bit is at 1, the first cp2 event and capture into cp has occurred. this bit cannot be set by program, only cleared. bit 4 = cmpien . compare int. enable . the com- pare interrupt is masked when this bit is 0. setting the bit to 1 enables the compare flag cmpflg to set the artimer interrupt. bit 3 = cmpflg . compare flag . when this bit is 0, no masked-compare true event has occurred since the last clear of this flag. if the bit is at 1, a masked-compare event has occurred. this bit cannot be set by program, only cleared. bit 2 = zeroien . compare to zero int enable. the masked-counter zero interrupt is masked when this bit is 0. setting the bit to 1 enables the zeroflg flag to set the artimer interrupt. bit 1 = zeroflg . compare to zero flag . when this bit is 0, no masked-counter zero event has occurred since the last clear of this flag. if the bit is at 1, a masked-counter zero event has occurred as the masked counter state equals 0 when run- ning or on hold (not on reset). bit 0 = pwmmd . pwm output mode control .the pwm output mode is set by this bit; when 0, the pwm output is run in set/reset mode (the pwm output is set on a masked-counter zero event and is reset when on a masked-compare event). when 1 the pwm output is in toggle mode; pwm toggles its state on every masked-compare event. notes : a masked-compare is the logical and of the mask register mask with the counter register ct, compared with the logical and of the compare register cmp: [(mask & ct) = (mask&cmp)]. a masked-counter zero is the logical and of the mask register mask with the counter register ct, compared with zero: [(mask & ct) = 0000h] 70 cp2pol cp2ien cp2flg cmpien cmflg zeroien zeroflg pwmmd 158
55/86 st62t32b st62e32b control registers (cont'd) status control register 4 (scr4) address: e3h - read/write/clear only bit7- bit4 = reserved, set to 0. bit 3 = ovfpol . overflow output polarity . this bit defines the polarity for the overflow output ovf. when 0, ovf is set on every overflow event if en- abled in set mode (ovfen = 1, ovfmd = 0). the reset state of ovf is 0. when 1, ovf is reset on every overflow event if enabled in set mode. the reset state of ovf is 1. bit 2 = ovfen . overflow output enable . this bit enables the overflow output ovf. when 0 the overflow output is disabled: if ovfpol = 0, the state of ovf is 0, if ovfpol = 1, the state of ovf = 1.the overflow output is enabled when this bit = 1, it must be set to use the ovf output. bit 1 = pwmpol . pwm output polarity. this bit defines the polarity for the pwm output pwm. when 0, pwm is set on every masked-counter zero event and is reset on a masked-compare if enabled in set/reset mode (pwmen = 1, pwm- md = 0). the reset state of pwm pin is 0 when 1, ovf is set on every masked-compare event and is reset on a masked-counter zero event if enabled in set/reset mode (pwmen = 1, pwmmd = 0). the reset state of pwm is 1. bit 0 = pwmen . pwm output enable. this bit en- ables the pwm output pwm. when 0 the pwm output is disabled: if pwmpol = 0, the state of pwm is 0, if pwmpol = 1, the state of pwm = 1. the pwm output is enabled when this bit = 1, it must be set to use the pwm output. notes : a masked-compare is the logical and of the mask register mask with the counter register ct, compared with the logical and of the compare register cmp: [(mask & ct) = (mask&cmp)]. a masked-counter zero is the logical and of the mask register mask with the counter register ct, compared with zero: [(mask & ct) = 0000h]. 4.3.6 16-bit registers note: care must be taken when using single-bit instructions (res/set/inc/dec) 16-bit registers (rlcp, cp, cmp, msk) since these instructions imply a read-modify-write operation on the register. as the st6 is based on a 8-bit architec- ture, to write a 16-bit register, the high byte must be written first to an intermediate register (latch register) and the whole 16-bit register is loaded at the same time as the low byte is written. a write operation of the high byte is performed on the in- termediate register (latch register) but a read op- eration of the high byte is directly performed on the 16-bit register (last loaded value). as a conse- quence, it is always mandatory to write the low byte before any single-bit instruction on the high byte in order to load the value set in the intermedi- ate register to the 16-bit register (refresh the 16-bit register). example: the following sequence is not good: ldi t16cmph, 055h ldi t16cmpl, 000h ; t16cmp (16-bit register )=5500h ldi t16cmph, 0aah ; t16cmp (16-bit register )=5500h inc t16cmph ; t16cmp (16-bit register )=5500h ldi t16cmpl, 000h ; t16cmp (16-bit register )=5600h ; and not ab00h the correct sequence is: ldi t16cmph, 055h ldi t16cmpl, 000h ; t16cmp (16-bit register )=5500h ldi t16cmph, 0aah ; t16cmp (16-bit register )=5500h ldi t16cmpl, 000h ; t16cmp (16-bit register )=aa00h inc t16cmph ; t16cmp (16-bit register )=aa00h ldi t16cmpl, 000h ;t16cmp (16-bit register )=ab00h 70 res. res. res. res. ovfpo l ovfen pmpol pwme n 159
56/86 st62t32b st62e32b reload/capture register high byte (rlcp) address: e9h - read/ (write if reload bit set) d7-d0. these bits are the high byte (d15-d8) of the 16-bit reload/capture register. reload/capture register low byte (rlcp) address: eah - read/ (write if reload bit set) d7-d0. these bits are the low byte (d7-d0) of the 16-bit reload/capture register. capture register high byte (cp) address: ebh - read only d7-d0. these bits are the high byte (d15-d8) of the 16-bit capture register. capture register low byte (cp) address: ech - read only d7-d0. these bits are the low byte (d7-d0) of the 16-bit capture register. compare register high byte (cmp) address: edh - read/write d7-d0. these bits are the high byte (d15-d8) of the 16-bit compare register. compare register low byte (cmp) address: eeh - read/write d7-d0. these bits are the low byte (d7-d0) of the 16-bit compare register. mask register high byte (mask) address: efh - read/write d7-d0. these bits are the high byte (d15-d8) of the 16-bit mask register. mask register low byte (mask) address: e0h - read/write d7-d0. these bits are the low byte (d7-d0) of the 16-bit mask register. 160
57/86 st62t32b st62e32b 4.4 a/d converter (adc) the a/d converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate i/o functions (the number of which is device depend- ent), offering 8-bit resolution with a selectable con- version time of 70us or 35 m s (at an oscillator clock frequency of 8mhz). the adc converts the input voltage by a process of successive approximations, using a clock fre- quency derived from the oscillator with a division factor of 12 or 6. after reset, division by 12 is used by default to insure compatibility with other mem- bers of the st62 mcu family. with an oscillator clock frequency less than 1.2mhz, conversion ac- curacy is decreased. selection of the input pin is done by configuring the related i/o line as an analog input via the op- tion and data registers (refer to i/o ports descrip- tion for additional information). only one i/o line must be configured as an analog input at any time. the user must avoid any situation in which more than one i/o pin is selected as an analog input si- multaneously, to avoid device malfunction. the adc uses two registers in the data space: the adc data conversion register, adr, which stores the conversion result, and the adc control regis- ter, adcr, used to program the adc functions. a conversion is started by writing a a1o to the start bit (sta) in the adc control register. this auto- matically clears (resets to a0o) the end of conver- sion bit (eoc). when a conversion is complete, the eoc bit is automatically set to a1o, in order to flag that conversion is complete and that the data in the adc data conversion register is valid. each conversion has to be separately initiated by writing to the sta bit. the sta bit is continuously scanned so that, if the user sets it to a1o while a previous conversion is in progress, a new conversion is started before com- pleting the previous one. the start bit (sta) is a write only bit, any attempt to read it will show a log- ical a0o. the a/d converter features a maskable interrupt associated with the end of conversion. the inter- rupt request occurs when the eoc bit is set (i.e. when a conversion is completed). the interrupt is masked using the eai (interrupt mask) bit in the control register. the power consumption of the device can be re- duced by turning off the adc peripheral. this is done by setting the pds bit in the adc control reg- ister to a0o. if pds=a1o, the a/d is powered and en- abled for conversion. this bit must be set at least one instruction before the beginning of the conver- sion to allow stabilisation of the a/d converter. this action is also needed before entering wait mode, since the a/d comparator is not automati- cally disabled in wait mode. during reset, any conversion in progress is stopped, the control register is reset to 40h and the adc interrupt is masked (eai=0). figure 34. adc block diagram 4.4.1 application notes the a/d converter does not feature a sample and hold circuit. the analog voltage to be measured should therefore be stable during the entire con- version cycle. voltage variation should not exceed 1/2 lsb for the optimum conversion accuracy. a low pass filter may be used at the analog input pins to reduce input voltage variation during con- version. when selected as an analog channel, the input pin is internally connected to a capacitor c ad of typi- cally 12pf. for maximum accuracy, this capacitor must be fully charged at the beginning of conver- sion. in the worst case, conversion starts one in- struction (6.5 m s) after the channel has been se- lected. in worst case conditions, the impedance, asi, of the analog voltage source is calculated us- ing the following formula: 6.5 m s=9xc ad x asi (capacitor charged to over 99.9%), i.e. 30 k w in- cluding a 50% guardband. asi can be higher if c ad has been charged for a longer period by adding in- structions before the start of conversion (adding more than 26 cpu cycles is pointless). control register converter va00418 result register reset interrupt clock av av dd ain 8 core control signals ss 8 core 161
58/86 st62t32b st62e32b a/d converter (cont'd) since the adc is on the same chip as the micro- processor, the user should not switch heavily load- ed output signals during conversion, if high preci- sion is required. such switching will affect the sup- ply voltages used as analog references. the accuracy of the conversion depends on the quality of the power supplies (v dd and v ss ). the user must take special care to ensure a well regu- lated reference voltage is present on the v dd and v ss pins (power supply voltage variations must be less than 5v/ms). this implies, in particular, that a suitable decoupling capacitor is used at the v dd pin. the converter resolution is given by: the input voltage (ain) which is to be converted must be constant for 1 m s before conversion and remain constant during conversion. conversion resolution can be improved if the pow- er supply voltage (v dd ) to the microcontroller is lowered. in order to optimise conversion resolution, the user can configure the microcontroller in wait mode, because this mode minimises noise disturbances and power supply variations due to output switch- ing. nevertheless, the wait instruction should be executed as soon as possible after the beginning of the conversion, because execution of the wait instruction may cause a small variation of the v dd voltage. the negative effect of this variation is min- imized at the beginning of the conversion when the converter is less sensitive, rather than at the end of conversion, when the less significant bits are determined. the best configuration, from an accuracy stand- point, is wait mode with the timer stopped. in- deed, only the adc peripheral and the oscillator are then still working. the mcu must be woken up from wait mode by the adc interrupt at the end of the conversion. it should be noted that waking up the microcontroller could also be done using the timer interrupt, but in this case the timer will be working and the resulting noise could affect conversion accuracy. a/d converter control register (adcr) address: 0d1h e read/write bit 7 = eai : enable a/d interrupt. if this bit is set to a1o the a/d interrupt is enabled, when eai=0 the interrupt is disabled. bit 6 = eoc : end of conversion. read only . this read only bit indicates when a conversion has been completed. this bit is automatically reset to a0o when the sta bit is written. if the user is using the interrupt option then this bit can be used as an interrupt pending bit. data in the data conversion register are valid only when this bit is set to a1o. bit 5 = sta : start of conversion. write only . writ- ing a a1o to this bit will start a conversion on the se- lected channel and automatically reset to a0o the eoc bit. if the bit is set again when a conversion is in progress, the present conversion is stopped and a new one will take place. this bit is write only, any attempt to read it will show a logical zero. bit 4 = pds : power down selection. this bit acti- vates the a/d converter if set to a1o. writing a a0o to this bit will put the adc in power down mode (idle mode). bit 3 = reserved. must be kept cleared bit 2= clsel: clock selection . when set, the adc is driven by the mcu internal clock divided by 6, and typical conversion time at 8mhz is 35 m s. when cleared (reset state), mcu clock divided by 12 is used with a typical 70 m s conversion time at 8mhz. bit 1-0: reserved. must be kept cleared. a/d converter data register (adr) address: 0d0h e read only bit 7-0 = d7-d0 : 8 bit a/d conversion result. v dd v ss 256 ---------------------------- 70 eai eoc sta pds d3 clsel d1 d0 70 d7 d6 d5 d4 d3 d2 d1 d0 162
59/86 st62t32b st62e32b 4.5 u. a. r. t. (universal asynchronous receiver/transmitter) the uart provides the basic hardware for asyn- chronous serial communication which, combined with an appropriate software routine, gives a serial interface providing communication with common baud rates (up to 38,400 baud with an 8mhz ex- ternal oscillator) and flexible character formats. operating in half-duplex mode only, the uart uses 11-bit characters comprising 1 start bit, 9 data bits and 1 stop bit. parity is supported by software only for transmit and for checking the received par- ity bit (bit 9). transmitted data is sent directly, while received data is buffered allowing further data characters to be received while the data is being read out of the receive buffer register. data trans- mit has priority over data being received. the uart is supplied with an mcu internal clock that is also available in wait mode of the processor. 4.5.1 ports interfacing rxd reception line and txd emission line are sharing the same external pins as two i/o lines. therefore, uart configuration requires to set these two i/o lines through the relevant ports reg- isters. the i/o line common with rxd line must be defined as input mode (with or without pull-up) while the i/o line common with txd line must be defined as output mode (push-pull or open drain). the transmitted data is inverted and can therefore use a single transistor buffering stage. defined as input, the rxd line can be read at any time as an i/o line during the uart operation. the txd pin follows i/o port registers value when uartoe bit is cleared, which means when no serial transmis- sion is in progress. as a consequence, a perma- nent high level has to be written onto the i/o port in order to achieve a proper stop condition on the txd line when no transmission is active. figure 35. uart block diagram control logic to core start dete ctor data shift register d8 d7 d6 d5 d4 d3 d2 d1 d0 control register baud rate receive buffer register programmable divider din dout d9 baud rate x 8 write read rxd1 txd1 uartoe rx and tx interrupts txd dr 0 mux 1 f osc vr02009 163
60/86 st62t32b st62e32b 4.5.2 clock generation the uart contains a built-in divider of the mcu internal clock for most common baud rates as shown in table 20. other baud rate values can be calculated from the chosen oscillator frequency di- vided by the divisor value shown. the divided clock provides a frequency that is 8 times the desired baud rate. this allows the data reception mechanism to provide a 2 to 1 majority voting system to determine the logic state of the asynchronous incoming serial logic bit by taking 3 timed samples within the 8 time states. the bits not sampled provide a buffer to compen- sate for frequency offsets between sender and re- ceiver. 4.5.3 data transmission transmission is fixed to a format of one start bit, nine data bits and one stop bit. the start and stop bits are automatically generated by the uart. the nine databits are under control of the user and are flexible in use. bits 0..7 are typically used as data bits while bit 9 is typically used as parity, but can also be a 9th data bit or an additional stop bit. as parity is not generated by the uart, it should be calculated by program and inserted in the appro- priate position of the data (i.e as bit 7 for 7-bit data, with bit 9 set to 1 giving two effective stop bits or as the independent bit 9). figure 36. data sampling points the character options are summarised in the fol- lowing table. table 19. character options bit 9 remains in the state programmed for consec- utive transmissions until changed by the user or until a character is received when the state of this bit is changed to that of the incoming bit 9. the recommended procedure is thus to set the value of this bit before transmission is started. transmission is started by writing to the data reg- ister (the baud rate and bit 9 should be set before this action). the uartoe signal switches the out- put multiplexer to the uart output and a start bit is sent (a 0 for one bit time) followed by the 8 data values (lsb first) and the value of the bit9 bit. the output is then set to 1 for a period of one bit time to generate a stop bit, and then the uartoe signal returns the txd1 line to its alternate i/o function. the end of transmission is flagged by setting txmt to 1 and an interrupt is generated if ena- bled. the txmt flag is reset by writing a 0 to the bit position, it is also cleared automatically when a new character is written to the data register. txmt can be set to 1 by software to generate a software interrupt so care must be taken in manip- ulating the control register. figure 37. character format vr02010 1 bit 012 345678 samples start bit 8 data 1 software parity 1 stop start bit 9 data no parity 1 stop start bit 8 data no parity 2 stop start bit 7 data 1 software parity 2 stop vr02012 position 1 28 10 bit bit start stop bit possible next character start d0 d1 d7 d8 start of data 9 164
61/86 st62t32b st62e32b 4.5.4 data reception the uart continuously looks for a falling edge on the input pin whenever a transmission is not ac- tive. once an edge is detected it waits 1 bit time (8 states) to accommodate the start bit, and then as- sembles the following serial data stream into the data register. the data in the ninth bit position is copied into bit 9, replacing any previous value set for transmission. after all 9 bits have been re- ceived, the receiver waits for the duration of one bit (for the stop bit) and then transfers the received data into the buffer register, allowing a following character to be received. the interrupt flag rxrdy is set to 1 as the data is transferred to the buffer register and, if enabled, will generate an in- terrupt. if a transmission is started during the course of a reception, the transmission takes priority and the reception is stopped to free the resources for the transmission. this implies that a handshaking sys- tem must be implemented, as polling of the uart to detect reception is not available. figure 38. uart data output 4.5.5 interrupt capabilities both reception and transmission processes can in- duce interrupt to the core as defined in the inter- rupt section. these interrupts are enabled by set- ting txien and rxien bit in the uartcr register, and txmt and rxrdy flags are set accordingly to the interrupt source. 4.5.6 registers uart data register (uartdr) address: d6h, read/write bit7-bit0. uart data bits . a write to this register loads the data into the transmit shift register and triggers the start of transmission. in addition this resets the transmit interrupt flag txmt. a read of this register returns the data from the receive buffer. warning . no read/write instructions may be used with this register as both transmit and receive share the same address table 20. baud rate selection txd1 txd port data 0 mux 1 output uartoe vr02011 70 d7 d6 d5 d4 d3 d2 d1 d0 br2 br2 br0 f int division baud rate f int = 8mhz f int = 4mhz 0 0 0 6.656 1200 600 0 0 1 3.328 2400 1200 0 1 0 1.664 4800 2400 0 1 1 832 9600 4800 1 0 0 416 19200 9600 1 0 1 256 31200 15600 1 1 0 208 38400 19200 1 1 1 reserved 165
62/86 st62t32b st62e32b registers (cont'd) uart control register (uartcr) address: d7h, read/write bit 7 = rxrdy. receiver ready . this flag be- comes active as soon as a complete byte has been received and copied into the receive buffer. it may be cleared by writing a zero to it. writing a one is possible. if the interrupt enable bit rxien is set to one, a software interrupt will be generated. bit 6 = txmt. transmitter empty . this flag be- comes active as soon as a complete byte has been sent. it may be cleared by writing a zero to it. it is automatically cleared by the action of writing a data value into the uart data register. bit 5 = rxien. receive interrupt enable . when this bit is set to 1, the receive interrupt is enabled. writing to rxien does not affect the status of the interrupt flag rxrdy. bit 4 = txien. transmit interrupt enable . when this bit is set to 1, the transmit interrupt is enabled. writing to txien does not affect the status of the interrupt flag txrdy. bit 3-1= br2..br0 . baudrate select . these bits select the operating baud rate of the uart, de- pending on the frequency of fosc. care should be taken not to change these bits during communica- tion as writing to these bits has an immediate ef- fect. bit 0 = dat9 . parity/data bit 9 . this bit represents the 9th bit of the data character that is received or transmitted. a write to this bit sets the level for the bit 9 to be transmitted, so it must always be set to the correct level before transmission. if used as parity, the value has first to be calculated by soft- ware. reading this bit will return the 9th bit of the received character. 70 rxrdy txmt rxien txie n br2 br1 br0 dat9 166
63/86 st62t32b st62e32b 4.6 serial peripheral interface (spi) the on-chip spi is an optimized serial synchro- nous interface that supports a wide range of indus- try standard spi specifications. the on-chip spi is controlled by small and simple user software to perform serial data exchange. the serial shift clock can be implemented either by software (us- ing the bit-set and bit-reset instructions), with the on-chip timer 1 by externally connecting the spi clock pin to the timer pin or by directly applying an external clock to the scl line. the peripheral is composed by an 8-bit data/shift register and a 4-bit binary counter while the sin pin is the serial shift input and sout is the serial shift output. these two lines can be tied together to implement two wires protocols (i c-b us, etc). when data is serialized, the msb is the first bit. sin has to be programmed as input. for serial output operation sout has to be programmed as open- drain output. the scl, sin and sout spi clock and data signals are connected to 3 i/o lines on the same external pins. with these 3 lines, the spi can operate in the following operating modes: software spi, s-bus, i c-bu s and as a standard serial i/o (clock, data, enable). an interrupt request can be generated af- ter eight clock pulses. figure 39 shows the spi block diagram. the scl line clocks, on the falling edge, the shift register and the counter. to allow spi operation in slave mode, the scl pin must be programmed as input and an external clock must be supplied to this pin to drive the spi peripheral. in master mode, scl is programmed as output, a clock signal must be generated by software to set and reset the port line. figure 39. spi block diagram set res clk reset 4-bit counter (q4=high after clock8) data reg direction i/o port 8-bit data shift register reset load dout output enable 8-bit tristate data i/o reset i/o port i/o port cp cp din d0....... .....................d 7 to processor data bus q4 q4 opr reg. din scl sin sout spi interrupt disable register spi data register data reg direction data reg direction dout write read mux 0 1 interrupt vr01504 167
64/86 st62t32b st62e32b serial peripheral interface (cont'd) after 8 clock pulses (d7..d0) the output q4 of the 4-bit binary counter becomes low, disabling the clock from the counter and the data/shift register. q4 enables the clock to generate an interrupt on the 8th clock falling edge as long as no reset of the counter (processor write into the 8-bit data/shift register) takes place. after a processor reset the interrupt is disabled. the interrupt is active when writing data in the shift register and desactivated when writing any data in the spi interrupt disable register. the generation of an interrupt to the core provides information that new data is available (input mode) or that transmission is completed (output mode), allowing the core to generate an acknowledge on the 9th clock pulse (i c-bu s). the interrupt is initiated by a high to low transition, and therefore interrupt options must be set accord- ingly as defined in the interrupt section. after power on reset, or after writing the data/shift register, the counter is reset to zero and the clock is enabled. in this condition the data shift register is ready for reception. no start condition has to be detected. through the user software the core may pull down the sin line (acknowledge) and slow down the scl, as long as it is needed to carry out data from the shift register. i c-bus master-slave, receiver-transmitter when pins sin and sout are externally connected together it is possible to use the spi as a receiver as well as a transmitter. through software routine (by using bit-set and bit-reset on i/o line) a clock can be generated allowing i c-bu s to work in mas- ter mode. when implementing an i c-bus protocol, the start condition can be detected by setting the processor into a wait for start condition by enabling the inter- rupt of the i/o port used for the sin line. this frees the processor from polling the sin and scl lines. after the transmission/reception the processor has to poll for the stop condition. in slave mode the user software can slow down the scl clock frequency by simply putting the scl i/o line in output open-drain mode and writing a zero into the corresponding data register bit. as it is possible to directly read the sin pin directly through the port register, the software can detect a difference between internal data and external data (master mode). similar condition can be applied to the clock. three (four) wire serial bus it is possible to use a single general purpose i/o pin (with the corresponding interrupt enabled) as a chip enable pin. scl acts as active or passive clock pin, sin as data in and sout as data out (four wire bus). sin and sout can be connected together externally to implement three wire bus. note : when the spi is not used, the three i/o lines (sin, scl, sout) can be used as normal i/o, with the fol- lowing limitation: bit sout cannot be used in open drain mode as this enables the shift register output to the port. it is recommended, in order to avoid spurious in- terrupts from the spi, to disable the spi interrupt (the default state after reset) i.e. no write must be made to the 8-bit shift register. an explicit interrupt disable may be made in software by a dummy write to the spi interrupt disable register. spi data/shift register address: ddh - read/write (sdsr) a write into this register enables spi interrupt after 8 clock pulses. spi interrupt disable register address: dch - read/write (sidr) a dummy write to this register disables spi inter- rupt. 70 d7 d6 d5 d4 d3 d2 d1 d0 70 d7 d6 d5 d4 d3 d2 d1 d0 168
65/86 st62t32b st62e32b 5 software 5.1 st6 architecture the st6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. the st6 core has the ability to set or clear any register or ram location bit of the data space with a single instruction. furthermore, the program may branch to a selected address depending on the status of any bit of the data space. the carry bit is stored with the value of the bit when the set or res instruction is processed. 5.2 addressing modes the st6 core offers nine addressing modes, which are described in the following paragraphs. three different address spaces are available: pro- gram space, data space, and stack space. pro- gram space contains the instructions which are to be executed, plus the data for immediate mode in- structions. data space contains the accumulator, the x,y,v and w registers, peripheral and in- put/output registers, the ram locations and data rom locations (for storage of tables and con- stants). stack space contains six 12-bit ram cells used to stack the return addresses for subroutines and interrupts. immediate . in the immediate addressing mode, the operand of the instruction follows the opcode location. as the operand is a rom byte, the imme- diate addressing mode is used to access con- stants which do not change during program execu- tion (e.g., a constant used to initialize a loop coun- ter). direct . in the direct addressing mode, the address of the byte which is processed by the instruction is stored in the location which follows the opcode. di- rect addressing allows the user to directly address the 256 bytes in data space memory with a single two-byte instruction. short direct . the core can address the four ram registers x,y,v,w (locations 80h, 81h, 82h, 83h) in the short-direct addressing mode. in this case, the instruction is only one byte and the selection of the location to be processed is contained in the op- code. short direct addressing is a subset of the di- rect addressing mode. (note that 80h and 81h are also indirect registers). extended . in the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four less significant bits of the opcode with the byte following the op- code. the instructions (jp, call) which use the extended addressing mode are able to branch to any address of the 4k bytes program space. an extended addressing mode instruction is two- byte long. program counter relative . the relative address- ing mode is only used in conditional branch in- structions. the instruction is used to perform a test and, if the condition is true, a branch with a span of -15 to +16 locations around the address of the rel- ative instruction. if the condition is not true, the in- struction which follows the relative instruction is executed. the relative addressing mode instruc- tion is one-byte long. the opcode is obtained in adding the three most significant bits which char- acterize the kind of the test, one bit which deter- mines whether the branch is a forward (when it is 0) or backward (when it is 1) branch and the four less significant bits which give the span of the branch (0h to fh) which must be added or sub- tracted to the address of the relative instruction to obtain the address of the branch. bit direct . in the bit direct addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode points to the ad- dress of the byte in which the specified bit must be set or cleared. thus, any bit in the 256 locations of data space memory can be set or cleared. bit test & branch . the bit test and branch ad- dressing mode is a combination of direct address- ing and relative addressing. the bit test and branch instruction is three-byte long. the bit iden- tification and the tested condition are included in the opcode byte. the address of the byte to be tested follows immediately the opcode in the pro- gram space. the third byte is the jump displace- ment, which is in the range of -127 to +128. this displacement can be determined using a label, which is converted by the assembler. indirect . in the indirect addressing mode, the byte processed by the register-indirect instruction is at the address pointed by the content of one of the in- direct registers, x or y (80h,81h). the indirect reg- ister is selected by the bit 4 of the opcode. a regis- ter indirect instruction is one byte long. inherent . in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. these instructions are one byte long. 169
66/86 st62t32b st62e32b 5.3 instruction set the st6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. they can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, jump/call, and bit manipulation. the following par- agraphs describe the different types. all the instructions belonging to a given type are presented in individual tables. load & store . these instructions use one, two or three bytes in relation with the addressing mode. one operand is the accumulator for load and the other operand is obtained from data memory using one of the addressing modes. for load immediate one operand can be any of the 256 data space bytes while the other is always immediate data. table 21. load & store instructions notes: x,y. indirect register pointers, v & w short direct registers # . immediate data (stored in rom memory) rr. data space register d . affected * . not affected instruction addressing mode bytes cycles flags zc ld a, x short direct 1 4 d * ld a, y short direct 1 4 d * ld a, v short direct 1 4 d * ld a, w short direct 1 4 d * ld x, a short direct 1 4 d * ld y, a short direct 1 4 d * ld v, a short direct 1 4 d * ld w, a short direct 1 4 d * ld a, rr direct 2 4 d * ld rr, a direct 2 4 d * ld a, (x) indirect 1 4 d * ld a, (y) indirect 1 4 d * ld (x), a indirect 1 4 d * ld (y), a indirect 1 4 d * ldi a, #n immediate 2 4 d * ldi rr, #n immediate 3 4 * * 170
67/86 st62t32b st62e32b instruction set (cont'd) arithmetic and logic . these instructions are used to perform the arithmetic calculations and logic operations. in and, add, cp, sub instruc- tions one operand is always the accumulator while the other can be either a data space memory con- tent or an immediate value in relation with the ad- dressing mode. in clr, dec, inc instructions the operand can be any of the 256 data space ad- dresses. in com, rlc, sla the operand is always the accumulator. table 22. arithmetic & logic instructions notes: x,y.indirect register pointers, v & w short direct registersd. affected # . immediate data (stored in rom memory)* . not affected rr. data space register instruction addressing mode bytes cycles flags zc add a, (x) indirect 1 4 dd add a, (y) indirect 1 4 dd add a, rr direct 2 4 dd addi a, #n immediate 2 4 dd and a, (x) indirect 1 4 dd and a, (y) indirect 1 4 dd and a, rr direct 2 4 dd andi a, #n immediate 2 4 dd clr a short direct 2 4 dd clr r direct 3 4 * * com a inherent 1 4 dd cp a, (x) indirect 1 4 dd cp a, (y) indirect 1 4 dd cp a, rr direct 2 4 dd cpi a, #n immediate 2 4 dd dec x short direct 1 4 d * dec y short direct 1 4 d * dec v short direct 1 4 d * dec w short direct 1 4 d * dec a direct 2 4 d * dec rr direct 2 4 d * dec (x) indirect 1 4 d * dec (y) indirect 1 4 d * inc x short direct 1 4 d * inc y short direct 1 4 d * inc v short direct 1 4 d * inc w short direct 1 4 d * inc a direct 2 4 d * inc rr direct 2 4 d * inc (x) indirect 1 4 d * inc (y) indirect 1 4 d * rlc a inherent 1 4 dd sla a inherent 2 4 dd sub a, (x) indirect 1 4 dd sub a, (y) indirect 1 4 dd sub a, rr direct 2 4 dd subi a, #n immediate 2 4 dd 171
68/86 st62t32b st62e32b instruction set (cont'd) conditional branch . the branch instructions achieve a branch in the program when the select- ed condition is met. bit manipulation instructions . these instruc- tions can handle any bit in data space memory. one group either sets or clears. the other group (see conditional branch) performs the bit test branch operations. control instructions . the control instructions control the mcu operations during program exe- cution. jump and call. these two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space. table 23. conditional branch instructions notes : b. 3-bit address rr. data space register e. 5 bit signed displacement in the range -15 to +16 d . affected. the tested bit is shifted into carry. ee. 8 bit signed displacement in the range -126 to +129 * . not affected table 24. bit manipulation instructions notes: b. 3-bit address; * . not affected rr. data space register; table 25. control instructions notes: 1. this instruction is deactivatedand a wai t is automatically executed instead of a stop if the watchdog function is selected. d . affected *. not affected table 26. jump & call instructions notes: abc. 12-bit address; * . not affected instruction branch if bytes cycles flags zc jrc e c = 1 1 2 * * jrnc e c = 0 1 2 * * jrze z=1 1 2 * * jrnz e z = 0 1 2 * * jrr b, rr, ee bit = 0 3 5 * d jrs b, rr, ee bit = 1 3 5 * d instruction addressing mode bytes cycles flags zc set b,rr bit direct 2 4 * * res b,rr bit direct 2 4 * * instruction addressing mode bytes cycles flags zc nop inherent 1 2 * * ret inherent 1 2 * * reti inherent 1 2 dd stop (1) inherent 1 2 * * wait inherent 1 2 * * instruction addressing mode bytes cycles flags zc call abc extended 2 4 * * jp abc extended 2 4 * * 172
69/86 st62t32b st62e32b opcode map summary. the following table contains an opcode map for the instructions used by the st6 low 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 low hi hi 0 0000 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 ld 0 0000 e abc e b0,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 0001 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 4 ldi 1 0001 e abc e b0,rr,ee e x e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 2 0010 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 cp 2 0010 e abc e b4,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 3 0011 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 4 cpi 3 0011 e abc e b4,rr,ee e a,x e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 4 0100 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 add 4 0100 e abc e b2,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 5 0101 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 4 addi 5 0101 e abc e b2,rr,ee e y e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 6 0110 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 inc 6 0110 e abc e b6,rr,ee e # e (x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 7 0111 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 7 0111 e abc e b6,rr,ee e a,y e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 8 1000 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 ld 8 1000 e abc e b1,rr,ee e # e (x),a 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 9 1001 2 rnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 9 1001 e abc e b1,rr,ee e v e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc a 1010 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 and a 1010 e abc e b5,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind b 1011 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 4 andi b 1011 e abc e b5,rr,ee e a,v e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm c 1100 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 sub c 1100 e abc e b3,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind d 1101 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 4 subi d 1101 e abc e b3,rr,ee e w e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm e 1110 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 dec e 1110 e abc e b7,rr,ee e # e (x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind f 1111 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc f 1111 e abc e b7,rr,ee e a,w e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc abbreviation s for addressing modes: legend: dir direct # indicates illegal instructions sd short direct e 5 bit displacement imm immediate b 3 bit address inh inherent rr 1byte dataspace address ext extended nn 1 byte immediate data b.d bit direct abc 12 bit address bt bit test ee 8 bit displacement pcr program counter relative ind indirect 2 jrc e 1 prc mnemonic addressing mode bytes cycle operand 173
70/86 st62t32b st62e32b opcode map summary (continued) low 8 1000 9 1001 a 1010 b 1011 c 1100 d 1101 e 1110 f 1111 low hi hi 0 0000 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 ldi 2 jrc 4 ld 0 0000 e abc e b0,rr e rr,nn e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind 1 0001 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 ld 1 0001 e abc e b0,rr e x e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 2 0010 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 com 2 jrc 4 cp 2 0010 e abc e b4,rr e a e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind 3 0011 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 cp 3 0011 e abc e b4,rr e x,a e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 4 0100 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 reti 2 jrc 4 add 4 0100 e abc e b2,rr e e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 5 0101 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 add 5 0101 e abc e b2,rr e y e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 6 0110 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 stop 2 jrc 4 inc 6 0110 e abc e b6,rr e e (y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 7 0111 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 inc 7 0111 e abc e b6,rr e y,a e rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 8 1000 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 jrc 4 ld 8 1000 e abc e b1,rr e # e (y),a 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind 9 1001 2 rnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 ld 9 1001 e abc e b1,rr e v e rr,a 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir a 1010 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 rcl 2 jrc 4 and a 1010 e abc e b5,rr e a e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind b 1011 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 and b 1011 e abc e b5,rr e v,a e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir c 1100 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 ret 2 jrc 4 sub c 1100 e abc e b3,rr e e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind d 1101 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 sub d 1101 e abc e b3,rr e w e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir e 1110 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 wait 2 jrc 4 dec e 1110 e abc e b7,rr e e (y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind f 1111 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 dec f 1111 e abc e b7,rr e w,a e rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir abbreviation s for addressing modes: legend: dir direct # indicates illegal instructions sd short direct e 5 bit displacement imm immediate b 3 bit address inh inherent rr 1byte dataspace address ext extended nn 1 byte immediate data b.d bit direct abc 12 bit address bt bit test ee 8 bit displacement pcr program counter relative ind indirect 2 jrc e 1 prc mnemonic addressing mode bytes cycle operand 174
71/86 st62t32b st62e32b 6 electrical characteristics 6.1 absolute maximum ratings this product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. for proper operation it is recommended that v i and v o be higher than v ss and lower than v dd . reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (v dd or v ss ). power considerations .the average chip-junc- tion temperature, tj, in celsius can be obtained from: tj=ta + pd x rthja where:ta = ambient temperature. rthja =package thermal resistance (junc- tion-to ambient). pd = pint + pport. pint =i dd xv dd (chip internal power). pport =port power dissipation (determined by the user). notes: - stresses above those listed as aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended period s may affect device reliability. - (1) within these limits , clamping diodes are guarantee to be not conductive. voltages outside these limits are authorised as long as injection current is kept within the specification. symbol parameter value unit v dd supply voltage -0.3 to 7.0 v v i input voltage v ss - 0.3 to v dd + 0.3 (1) v v o output voltage v ss - 0.3 to v dd + 0.3 (1) v i o current drain per pin excluding v dd ,v ss 10 ma iv dd total current into v dd (source) 50 ma iv ss total current out of v ss (sink) 50 ma tj junction temperature 150 c t stg storage temperature -60 to 150 c 175
72/86 st62t32b st62e32b 6.2 recommended operating conditions notes : 1. care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the a/d conversion. for a -1ma injection, a maximum 10 k w is recommended. 2. an oscillator frequency above 1mhz is recommended for reliable a/d results. figure 40. maximum operating frequency (f max ) versus supply voltage (v dd ) the shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions. symbol parameter test condition s value unit min. typ. max. t a operating temperature 6 suffix version 1 suffix version 3 suffix version -40 0 -40 85 70 125 c v dd operating supply voltage f osc = 2mhz fosc= 8mhz 3.0 4.5 6.0 6.0 v f osc oscillator frequency 2) v dd =3v v dd = 4.5v, 1 & 6 suffix v dd = 4.5v, 3 suffix 0 0 0 4.0 8.0 4.0 mhz f osg internal frequency with osg enable 2) v dd =3v v dd = 4.5v 2 4 f osc f osc mhz i inj+ pin injection current (positive) v dd = 4.5 to 5.5v +5 ma i inj- pin injection current (negative) v dd = 4.5 to 5.5v -5 ma 8 7 6 5 4 3 2 1 2.5 3 3.5 4 4.5 5 5.5 6 supply voltage (v dd ) maximum frequ ency (mhz) functionality is not guaranteed in this area 3 suffix version 1 & 6 suffix version f osg min 176
73/86 st62t32b st62e32b 6.3 dc electrical characteristics (t a = -40 to +125 c unless otherwise specified) notes: (1) hysteresis voltage between switching levels (2) all peripherals running (3) all peripherals in stand-by (t a = -40 to +85 c unless otherwise specified) symbol parameter test cond itions value unit min. typ. max. v il input low level voltage all input pins v dd x 0.3 v v ih input high level voltage all input pins v dd x 0.7 v v hys hysteresis voltage (1) all input pins v dd =5v v dd =3v 0.2 0.2 v v ol low level output voltage all output pins v dd = 5.0v; i ol =+10 m a v dd = 5.0v; i ol = + 3ma 0.1 0.8 v low level output voltage 20 ma sink i/o pins v dd = 5.0v; i ol =+10 m a v dd = 5.0v; i ol = +7ma v dd = 5.0v; i ol = +15ma 0.1 0.8 1.3 v oh high level output voltage all output pins v dd = 5.0v; i ol =-10 m a v dd = 5.0v; i ol = -3.0ma 4.9 3.5 v r pu pull-up resistance all input pins 40 100 200 kw reset pin 150 350 900 i il i ih input leakage current all input pins but reset v in =v ss (no pull-up configured) v in =v dd 0.1 1.0 m a input leakage current reset pin v in =v ss v in =v dd -8 -16 -30 10 i dd supply current in reset mode v reset =v ss f osc =8mhz 7ma supply current in run mode (2) v dd =5.0v f int =8mhz, t a <85 c7ma supply current in wait mode (3) v dd =5.0v f int =8mhz, t a <85 c2ma supply current in stop mode (3) i load = 0ma v dd = 5.0v 20 m a symbol parameter test cond itions value unit min. typ. max. v ol low level output voltage all output pins v dd = 5.0v; i ol =+10 m a v dd = 5.0v; i ol = + 5ma 0.1 0.8 v low level output voltage 20 ma sink i/o pins v dd = 5.0v; i ol =+10 m a v dd = 5.0v; i ol = +10ma v dd = 5.0v; i ol = +20ma 0.1 0.8 1.3 v oh high level output voltage all output pins v dd = 5.0v; i ol =-10 m a v dd = 5.0v; i ol = -5.0ma 4.9 3.5 v i dd supply current in stop mode i load = 0ma v dd = 5.0v 10 m a 177
74/86 st62t32b st62e32b 6.4 ac electrical characteristics (t a = -40 to +125 c unless otherwise specified) note : 1. period for which v dd has to be connected at 0v to allow internal reset function at next power-up. 6.5 a/d converter characteristics (t a = -40 to +125 c unless otherwise specified) notes : 1. noise at av dd ,av ss <10mv 2. wit h oscillator frequencies less than 1mhz, the a/d converter accuracy is decreased. symbol parameter test conditions value unit min. typ. max. t rec supply recovery time (1) 100 ms t wr minimum pulse width (v dd =5v) reset pin nmi pin 100 100 ns t wee eeprom write time t a =25 c t a =85 c t a = 125 c 5 10 20 10 20 30 ms endurance eeprom write/erase cycle q a l ot acceptance 300,000 1 million cycles retention eeprom data retention t a =55 c 10 years c in input capacitance all inputs pins 10 pf c out output capacitance all outputs pins 10 pf symbol parameter test condit ions value unit min. typ. max. res resolution 8 bit a tot total accuracy (1) (2) f osc > 1.2mhz f osc > 32khz 2 4 lsb t c conversion time f osc = 8mhz, t a <85 c f osc = 4mhz 70 140 m s zir zero input reading conversion result when v in =v ss 00 hex fsr full scale reading conversion result when v in =v dd ff hex ad i analog input current during conversion v dd = 4.5v 1.0 m a ac in analog input capacitance 2 5 pf 178
75/86 st62t32b st62e32b 6.6 timer characteristics (t a = -40 to +125 c unless otherwise specified) 6.7 spi characteristics (t a = -40 to +125 c unless otherwise specified) 6.8 artimer16 electrical characteristics (t a = -40 to +125 c unless otherwise specified) symbol parameter test condi tions value unit min. typ. max. f in input frequency on timer pin mhz t w pulse width at timer pin v dd = 3.0v v dd > 4.5v 1 125 m s ns symbol parameter test conditions value unit min. typ. max. f cl clock frequency applied on scl 1 mhz t su set-up time applied on sin 50 ns t h hold time applied on sin 100 ns symbol parameter test condit ions value unit min typ max f in input frequency on cp1, cp2 pins mhz t w pulse width at cp1, cp2 pins v dd = 3.0v v dd > 4.5v 1 125 m s ns 179
76/86 st62t32b st62e32b 7 general information 7.1 package mechanical data figure 41. 42-pin plastic shrink dual-in-line package figure 42. 52-pin plastic quad flat package dim. mm inches min typ max min typ max a 5.08 0.200 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.46 0.56 0.018 0.022 b2 1.02 1.14 0.040 0.045 c 0.23 0.25 0.38 0.009 0.010 0.015 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.600 0.630 e1 12.70 13.72 14.48 0.500 0.540 0.570 e 1.78 0.070 ea 15.24 0.600 eb 18.54 0.730 ec 1.52 0.000 0.060 l 2.54 3.30 3.56 0.100 0.130 0.140 number of pins n42 pdip42s dim mm inches min typ max min typ max a 3.40 0.134 a1 0.25 0.010 a2 2.55 2.80 3.05 0.100 0.110 0.120 b 0.35 0.50 0.014 0.020 c 0.13 0.23 0.005 0.009 d 16.95 17.20 17.45 0.667 0.677 0.687 d1 13.90 14.00 14.10 0.547 0.551 0.555 d3 12.00 0.472 e 16.95 17.20 17.45 0.667 0.677 0.687 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 12.00 0.472 e 1.00 0.039 k 0 7 0 7 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 m number of pins n 52 pqfp52 180
77/86 st62t32b st62e32b package mechanical data (cont'd) figure 43. 42-pin ceramic shrink dual-in-line package thermal characteristic symbol parameter test conditions value unit min. typ. max. rthja thermal resistance sdip42 70 c/w qfp52 70 dim. mm inches min typ max min typ max a 4.01 0.158 a1 0.76 0.030 b 0.38 0.46 0.56 0.015 0.018 0.022 b1 0.76 0.89 1.02 0.030 0.035 0.040 c 0.23 0.25 0.38 0.009 0.010 0.015 d 36.68 37.34 38.00 1.444 1.470 1.496 d1 35.56 1.400 e1 14.48 14.99 15.49 0.570 0.590 0.610 e 1.78 0.070 g 14.12 14.38 14.63 0.556 0.566 0.576 g1 18.69 18.95 19.20 0.736 0.746 0.756 g2 1.14 0.045 g3 11.05 11.30 11.56 0.435 0.445 0.455 g4 15.11 15.37 15.62 0.595 0.605 0.615 l 2.92 5.08 0.115 0.200 s 0.89 0.035 number of pins n42 cdip42sw 181
78/86 st62t32b st62e32b 7.2 ordering information table 27. otp/eprom version ordering information sales type program memory (bytes) i/o temperature range package ST62E32BF1 7948 (eprom) 30 0to70 c sdip42w st62t32bb6 st62t32bb3 7948 (otp) -40 to 85 c -40 to 125 c sdip42w st62t32bq6 st62t32bq3 -40 to 85 c -40 to 125 c pqfp52 182
september 1998 79/86 rev. 2.5 st62p32b 8-bit fastrom mcus with a/d converter, 16 bit auto-reload timer, eeprom, spi and uart n 3.0 to 6.0v supply operating range n 8 mhz maximum clock frequency n -40 to +125 c operating temperature range n run, wait and stop modes n 5 interrupt vectors n look-up table capability in program memory n data storage in program memory: user selectable size n data ram: 192 bytes n data eeprom: 128 bytes n 30 i/o pins, fully programmable as: input with pull-up resistor input without pull-up resistor input with interrupt generation open-drain or push-pull output analog input n 9 i/o lines can sink up to 20ma to drive leds or triacs directly n 8-bit timer/ counter with 7-bit programmable prescaler n 16-bit auto-reload timer with 7-bit programmable prescaler (ar timer) n digital watchdog n 8-bit a/d converter with 21 analog inputs n 8-bit synchronous peripheral interface (spi) n 8-bit asynchronous peripheral interface (uart) n on-chip clock oscillator can be driven by quartz crystal or ceramic resonator n oscillator safe guard n one external non-maskable interrupt n st623x-emu2 emulation and development system (connects to an ms-dos pc via a parallel port). device summary device rom (bytes) i/o pins st62p32b 7948 30 (see end of datasheet for ordering information) psdip42 pqfp52 183
80/86 st62p32b 1 general description 1.1 introduction the st62p32b is the f actory a dvanced s ervice t echnique rom (fastrom) versions of st62t32b otp devices. they offer the same functionality as otp devices, selecting as fastrom options the options de- fined in the programmable option byte of the otp version. 1.2 ordering information the following section deals with the procedure for transfer of customer codes to stmicroelectronics. 1.2.1 transfer of customer code customer code is made up of the rom contents and the list of the selected fastrom options. the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmi- croelectronics using the correctly filled option list appended. 1.2.2 listing generation and verification when stmicroelectronics receives the user's rom contents, a computer listing is generated from it. this listing refers exactly to the rom con- tents and options which will be used to produce the specified mcu. the listing is then returned to the customer who must thoroughly check, com- plete, sign and return it to stmicroelectronics. the signed listing forms a part of the contractual agree- ment for the production of the specific customer mcu. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. table 1. rom memory map for st62p32b table 2. fastrom version ordering information (*) advanced information rom page device address description page 0 0000h-007fh 0080h-07ffh reserved user rom page 1 astatico 0800h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh user rom reserved interrupt vectors reserved nmi vector reset vector page 2 0000h-000fh 0010h-07ffh reserved user rom page 3 0000h-000fh 0010h-07ffh reserved user rom sales type rom i/o temperature range package st62p32bb1/xxx st62p32bb6/xxx st62p32bb3/xxx (*) 7948 30 0 to +70 c -40 to 85 c -40 to 125 c sdip42 st62p32bq1/xxx st62p32bq6/xxx st62p32bq3/xxx (*) 0 to +70 c -40 to 85 c -40 to 125 c pqfp52 184
81/86 st62p32b st62p32b fastrom microcontroller option list customer address contact phone no reference stmicroelectronics references device: [ ] st62p32b package: [ ] dual in line plastic[ ] plastic quad flat (tape & reel) temperature range: [ ] 0 cto+70 c[]-40 cto+85 c watchdog selection: [ ] software activation [ ] hardware activation ports pull-up selection: [ ] yes [ ] no nmi pull-up selection: [ ] yes [ ] no timer pull-up selection: [ ] yes [ ] no external stop mode control:[ ] enabled [ ] disabled osg: []enabled [ ] disabled readout protection: [ ] standard []enabled comments : supply operating range in the application: oscillator fequency in the application: notes . . . . . . . . . . . . . . . . . . signature date 185
82/86 st62p32b notes: 186
september 1998 83/86 rev. 2.5 st6232b 8-bit mcus with a/d converter, 16 bit auto-reload timer, eeprom, spi and uart n 3.0 to 6.0v supply operating range n 8 mhz maximum clock frequency n -40 to +125 c operating temperature range n run, wait and stop modes n 5 interrupt vectors n look-up table capability in program memory n data storage in program memory: user selectable size n data ram: 192 bytes n data eeprom: 128 bytes n 30 i/o pins, fully programmable as: input with pull-up resistor input without pull-up resistor input with interrupt generation open-drain or push-pull output analog input n 9 i/o lines can sink up to 20ma to drive leds or triacs directly n 8-bit timer/ counter with 7-bit programmable prescaler n 16-bit auto-reload timer with 7-bit programmable prescaler (ar timer) n digital watchdog n 8-bit a/d converter with 21 analog inputs n 8-bit synchronous peripheral interface (spi) n 8-bit asynchronous peripheral interface (uart) n on-chip clock oscillator can be driven by quartz crystal or ceramic resonator n oscillator safe guard n one external non-maskable interrupt n st623x-emu2 emulation and development system (connects to an ms-dos pc via a parallel port). device summary device rom (bytes) i/o pins st6232b 7948 30 (see end of datasheet for ordering information) psdip42 pqfp52 187
84/86 st6232b 1 general description 1.1 introduction the st6232b is mask programmed rom version of st62t32b otp devices. they offer the same functionality as otp devices, selecting as rom options the options defined in the programmable option byte of the otp version. figure 1. programming wave form 1.2 rom readout protection if the rom readout protection option is selected, a protection fuse can be blown to pre- vent any access to the program memory content. in case the user wants to blow this fuse, high volt- age must be applied on the test pin. figure 2. programming circuit note: zpd15 is used for overvoltage protection 0.5s min test 15 14v typ 10 5 test 100ma 4ma typ vr02001 max 150 m s typ t vr02003 test 5v 100nf 47mf protect 100nf v dd v ss zpd15 15v 14v 188
85/86 st6232b st6232b microcontroller option list customer address contact phone no reference stmicroelectronics references device: [ ] st6232b package: [ ] dual in line plastic[ ] plastic quad flat (tape & reel) temperature range: [ ] 0 cto+70 c[]-40 cto+85 c special marking: [ ] no [ ] yes o_ _ _ _ _ _ _ _ _ _ _ o authorized characters are letters, digits, '.', '-', '/' and spaces only. maximum character count:sdip42: 10 pqfp52: 10 watchdog selection: [ ] software activation [ ] hardware activation ports pull-up selection: [ ] yes [ ] no nmi pull-up selection: [ ] yes [ ] no timer pull-up selection: [ ] yes [ ] no external stop mode control:[ ] enabled [ ] disabled osg: []enabled [ ] disabled rom readout protection:[ ] standard (fuse cannot be blown) [ ] enabled (fuse can be blown by the customer) note: no part is delivered with protected rom. the fuse must be blown for protection to be effective. comments : supply operating range in the application: oscillator fequency in the application: notes . . . . . . . . . . . . . . . . . . signature date 189
86/86 st6232b 1.3 ordering information the following section deals with the procedure for transfer of customer codes to stmicroelectronics. 1.3.1 transfer of customer code customer code is made up of the rom contents and the list of the selected mask options. the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file gener- ated by the development tool. all unused bytes must be set to ffh. the selected mask options are communicated to stmicroelectronics using the correctly filled op- tion list appended. 1.3.2 listing generation and verification when stmicroelectronics receives the user's rom contents, a computer listing is generated from it. this listing refers exactly to the mask which will be used to produce the specified mcu. the listing is then returned to the customer who must thoroughly check, complete, sign and return it to stmicroelectronics. the signed listing forms a part of the contractual agreement for the creation of the specific customer mask. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. table 1. rom memory map for st6232b table 2. rom version ordering information information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http:/ /www.st.com rom page device address description page 0 0000h-007fh 0080h-07ffh reserved user rom page 1 astatico 0800h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh user rom reserved interrupt vectors reserved nmi vector reset vector page 2 0000h-000fh 0010h-07ffh reserved user rom page 3 0000h-000fh 0010h-07ffh reserved user rom sales type rom i/o temperature range package st6232bb1/xxx st6232bb6/xxx st6232bb3/xxx 7948 30 0 to +70 c -40 to 85 c -40 to 125 c sdip42 st6232bq1/xxx st6232bq6/xxx st6232bq3/xxx 0 to +70 c -40 to 85 c -40 to 125 c pqfp52 190

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